tt.map.rpt

Verilog 经典实例

; Add Pass-Through Logic to Inferred RAMs                                        ; On                 ; On                 ;
; Parallel Synthesis                                                             ; Off                ; Off                ;
; NOT Gate Push-Back                                                             ; On                 ; On                 ;
; Power-Up Don't Care                                                            ; On                 ; On                 ;
; Remove Redundant Logic Cells                                                   ; Off                ; Off                ;
; Remove Duplicate Registers                                                     ; On                 ; On                 ;
; Ignore CARRY Buffers                                                           ; Off                ; Off                ;
; Ignore CASCADE Buffers                                                         ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                                          ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                                      ; Off                ; Off                ;
; Ignore LCELL Buffers                                                           ; Off                ; Off                ;
; Ignore SOFT Buffers                                                            ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                                 ; Off                ; Off                ;
; Optimization Technique -- Cyclone                                              ; Balanced           ; Balanced           ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II/Cyclone III ; 70                 ; 70                 ;
; Auto Carry Chains                                                              ; On                 ; On                 ;
; Auto Open-Drain Pins                                                           ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                                          ; Off                ; Off                ;
; Perform gate-level register retiming                                           ; Off                ; Off                ;
; Allow register retiming to trade off Tsu/Tco with Fmax                         ; On                 ; On                 ;
; Auto ROM Replacement                                                           ; On                 ; On                 ;
; Auto RAM Replacement                                                           ; On                 ; On                 ;
; Auto Shift Register Replacement                                                ; Auto               ; Auto               ;
; Auto Clock Enable Replacement                                                  ; On                 ; On                 ;
; Allow Synchronous Control Signals                                              ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                                         ; Off                ; Off                ;
; Auto RAM Block Balancing                                                       ; On                 ; On                 ;
; Auto RAM to Logic Cell Conversion                                              ; Off                ; Off                ;
; Auto Resource Sharing                                                          ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                             ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                             ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                                  ; Off                ; Off                ;
; Ignore translate_off and synthesis_off directives                              ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report                             ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                             ; Off                ; Off                ;
; Retiming Meta-Stability Register Sequence Length                               ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                                   ; Normal compilation ; Normal compilation ;
; HDL message level                                                              ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                                ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                       ; 100                ; 100                ;
; Clock MUX Protection                                                           ; On                 ; On                 ;
; Block Design Naming                                                            ; Auto               ; Auto               ;
+--------------------------------------------------------------------------------+--------------------+--------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                         ;
+----------------------------------+-----------------+------------------------------------+----------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path                                         ;
+----------------------------------+-----------------+------------------------------------+----------------------------------------------------------------------+
; tt.bdf                           ; yes             ; User Block Diagram/Schematic File  ; G:/Q71/2c5_v5/AD_TLC549_TEST/tt.bdf                                  ;
; ADC_TLC549.v                     ; yes             ; User Verilog HDL File              ; G:/Q71/2c5_v5/AD_TLC549_TEST/ADC_TLC549.v                            ;
; bin27seg.v                       ; yes             ; User Verilog HDL File              ; G:/Q71/2c5_v5/AD_TLC549_TEST/bin27seg.v                              ;
; lpm_mult.tdf                     ; yes             ; Megafunction                       ; g:/altera/72/quartus/libraries/megafunctions/lpm_mult.tdf            ;
; aglobal72.inc                    ; yes             ; Megafunction                       ; g:/altera/72/quartus/libraries/megafunctions/aglobal72.inc           ;
; lpm_add_sub.inc                  ; yes             ; Megafunction                       ; g:/altera/72/quartus/libraries/megafunctions/lpm_add_sub.inc         ;
; multcore.inc                     ; yes             ; Megafunction                       ; g:/altera/72/quartus/libraries/megafunctions/multcore.inc            ;
; bypassff.inc                     ; yes             ; Megafunction                       ; g:/altera/72/quartus/libraries/megafunctions/bypassff.inc            ;
; altshift.inc                     ; yes             ; Megafunction                       ; g:/altera/72/quartus/libraries/megafunctions/altshift.inc            ;
; multcore.tdf                     ; yes             ; Megafunction                       ; g:/altera/72/quartus/libraries/megafunctions/multcore.tdf            ;
; csa_add.inc                      ; yes             ; Megafunction                       ; g:/altera/72/quartus/libraries/megafunctions/csa_add.inc             ;
; mpar_add.inc                     ; yes             ; Megafunction                       ; g:/altera/72/quartus/libraries/megafunctions/mpar_add.inc            ;
; muleabz.inc                      ; yes             ; Megafunction                       ; g:/altera/72/quartus/libraries/megafunctions/muleabz.inc             ;
; mul_lfrg.inc                     ; yes             ; Megafunction                       ; g:/altera/72/quartus/libraries/megafunctions/mul_lfrg.inc            ;
; mul_boothc.inc                   ; yes             ; Megafunction                       ; g:/altera/72/quartus/libraries/megafunctions/mul_boothc.inc          ;
; alt_ded_mult.inc                 ; yes             ; Megafunction                       ; g:/altera/72/quartus/libraries/megafunctions/alt_ded_mult.inc        ;
; alt_ded_mult_y.inc               ; yes             ; Megafunction                       ; g:/altera/72/quartus/libraries/megafunctions/alt_ded_mult_y.inc      ;
; dffpipe.inc                      ; yes             ; Megafunction                       ; g:/altera/72/quartus/libraries/megafunctions/dffpipe.inc             ;
; mpar_add.tdf                     ; yes             ; Megafunction                       ; g:/altera/72/quartus/libraries/megafunctions/mpar_add.tdf            ;
; lpm_add_sub.tdf                  ; yes             ; Megafunction                       ; g:/altera/72/quartus/libraries/megafunctions/lpm_add_sub.tdf         ;
; addcore.inc                      ; yes             ; Megafunction                       ; g:/altera/72/quartus/libraries/megafunctions/addcore.inc             ;
; look_add.inc                     ; yes             ; Megafunction                       ; g:/altera/72/quartus/libraries/megafunctions/look_add.inc            ;
; alt_stratix_add_sub.inc          ; yes             ; Megafunction                       ; g:/altera/72/quartus/libraries/megafunctions/alt_stratix_add_sub.inc ;
; alt_mercury_add_sub.inc          ; yes             ; Megafunction                       ; g:/altera/72/quartus/libraries/megafunctions/alt_mercury_add_sub.inc ;
; addcore.tdf                      ; yes             ; Megafunction                       ; g:/altera/72/quartus/libraries/megafunctions/addcore.tdf             ;
; a_csnbuffer.inc                  ; yes             ; Megafunction                       ; g:/altera/72/quartus/libraries/megafunctions/a_csnbuffer.inc         ;
; a_csnbuffer.tdf                  ; yes             ; Megafunction                       ; g:/altera/72/quartus/libraries/megafunctions/a_csnbuffer.tdf         ;
; altshift.tdf                     ; yes             ; Megafunction                       ; g:/altera/72/quartus/libraries/megafunctions/altshift.tdf            ;
; lpm_divide.tdf                   ; yes             ; Megafunction                       ; g:/altera/72/quartus/libraries/megafunctions/lpm_divide.tdf          ;
; abs_divider.inc                  ; yes             ; Megafunction                       ; g:/altera/72/quartus/libraries/megafunctions/abs_divider.inc         ;
; sign_div_unsign.inc              ; yes             ; Megafunction                       ; g:/altera/72/quartus/libraries/megafunctions/sign_div_unsign.inc     ;
; db/lpm_divide_q6m.tdf            ; yes             ; Auto-Generated Megafunction        ; G:/Q71/2c5_v5/AD_TLC549_TEST/db/lpm_divide_q6m.tdf                   ;
; db/sign_div_unsign_mlh.tdf       ; yes             ; Auto-Generated Megafunction        ; G:/Q71/2c5_v5/AD_TLC549_TEST/db/sign_div_unsign_mlh.tdf              ;
; db/alt_u_div_sqe.tdf             ; yes             ; Auto-Generated Megafunction        ; G:/Q71/2c5_v5/AD_TLC549_TEST/db/alt_u_div_sqe.tdf                    ;
; db/add_sub_3dc.tdf               ; yes             ; Auto-Generated Megafunction        ; G:/Q71/2c5_v5/AD_TLC549_TEST/db/add_sub_3dc.tdf                      ;
; db/add_sub_4dc.tdf               ; yes             ; Auto-Generated Megafunction        ; G:/Q71/2c5_v5/AD_TLC549_TEST/db/add_sub_4dc.tdf                      ;
; db/add_sub_7dc.tdf               ; yes             ; Auto-Generated Megafunction        ; G:/Q71/2c5_v5/AD_TLC549_TEST/db/add_sub_7dc.tdf                      ;
; db/add_sub_5dc.tdf               ; yes             ; Auto-Generated Megafunction        ; G:/Q71/2c5_v5/AD_TLC549_TEST/db/add_sub_5dc.tdf                      ;
; db/add_sub_6dc.tdf               ; yes             ; Auto-Generated Megafunction        ; G:/Q71/2c5_v5/AD_TLC549_TEST/db/add_sub_6dc.tdf                      ;
; db/add_sub_59c.tdf               ; yes             ; Auto-Generated Megafunction        ; G:/Q71/2c5_v5/AD_TLC549_TEST/db/add_sub_59c.tdf                      ;
; db/lpm_divide_tul.tdf            ; yes             ; Auto-Generated Megafunction        ; G:/Q71/2c5_v5/AD_TLC549_TEST/db/lpm_divide_tul.tdf                   ;