tt.map.rpt

Verilog 经典实例

Analysis & Synthesis report for tt
Fri Jan 11 02:18:31 2008
Quartus II Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version


---------------------
; Table of Contents ;
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  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Registers Removed During Synthesis
  8. General Register Statistics
  9. Multiplexer Restructuring Statistics (Restructuring Performed)
 10. Source assignments for bin27seg:inst1|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder
 11. Parameter Settings for User Entity Instance: ADC_TLC549:inst
 12. Parameter Settings for Inferred Entity Instance: bin27seg:inst1|lpm_mult:Mult0
 13. Parameter Settings for Inferred Entity Instance: bin27seg:inst1|lpm_divide:Div0
 14. Parameter Settings for Inferred Entity Instance: bin27seg:inst1|lpm_divide:Mod1
 15. Parameter Settings for Inferred Entity Instance: bin27seg:inst1|lpm_divide:Div1
 16. Parameter Settings for Inferred Entity Instance: bin27seg:inst1|lpm_divide:Mod2
 17. Parameter Settings for Inferred Entity Instance: bin27seg:inst1|lpm_divide:Mod0
 18. Parameter Settings for Inferred Entity Instance: bin27seg:inst1|lpm_divide:Div2
 19. Parameter Settings for Inferred Entity Instance: bin27seg:inst1|lpm_divide:Mod3
 20. lpm_mult Parameter Settings by Entity Instance
 21. Analysis & Synthesis Messages
 22. Analysis & Synthesis Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-----------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                ;
+-----------------------------+-----------------------------------------------+
; Analysis & Synthesis Status ; Successful - Fri Jan 11 02:18:31 2008         ;
; Quartus II Version          ; 7.2 Build 175 11/20/2007 SP 1 SJ Full Version ;
; Revision Name               ; tt                                            ;
; Top-level Entity Name       ; tt                                            ;
; Family                      ; Cyclone                                       ;
; Total logic elements        ; 608                                           ;
; Total pins                  ; 21                                            ;
; Total virtual pins          ; 0                                             ;
; Total memory bits           ; 0                                             ;
; DSP block 9-bit elements    ; 0                                             ;
; Total PLLs                  ; 0                                             ;
; Total DLLs                  ; 0                                             ;
+-----------------------------+-----------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                            ;
+--------------------------------------------------------------------------------+--------------------+--------------------+
; Option                                                                         ; Setting            ; Default Value      ;
+--------------------------------------------------------------------------------+--------------------+--------------------+
; Device                                                                         ; EP1C6Q240C8        ;                    ;
; Top-level entity name                                                          ; tt                 ; tt                 ;
; Family name                                                                    ; Cyclone            ; Stratix            ;
; Use smart compilation                                                          ; Off                ; Off                ;
; Maximum processors allowed for parallel compilation                            ; 1                  ; 1                  ;
; Restructure Multiplexers                                                       ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                            ; Off                ; Off                ;
; Preserve fewer node names                                                      ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                                      ; Off                ; Off                ;
; Verilog Version                                                                ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                                   ; VHDL93             ; VHDL93             ;
; State Machine Processing                                                       ; Auto               ; Auto               ;
; Safe State Machine                                                             ; Off                ; Off                ;
; Extract Verilog State Machines                                                 ; On                 ; On                 ;
; Extract VHDL State Machines                                                    ; On                 ; On                 ;
; Ignore Verilog initial constructs                                              ; Off                ; Off                ;