i2c_fpga.map.qmsg

Verilog 经典实例

{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "i2c:inst4\|addr\[0\] data_in GND " "Warning: Reduced register \"i2c:inst4\|addr\[0\]\" with stuck data_in port to stuck value GND" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 699 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "i2c:inst4\|writeData_reg\[7\] data_in GND " "Warning: Reduced register \"i2c:inst4\|writeData_reg\[7\]\" with stuck data_in port to stuck value GND" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 699 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "i2c:inst4\|writeData_reg\[6\] data_in GND " "Warning: Reduced register \"i2c:inst4\|writeData_reg\[6\]\" with stuck data_in port to stuck value GND" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 699 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "i2c:inst4\|writeData_reg\[5\] data_in GND " "Warning: Reduced register \"i2c:inst4\|writeData_reg\[5\]\" with stuck data_in port to stuck value GND" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 699 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "i2c:inst4\|writeData_reg\[4\] data_in GND " "Warning: Reduced register \"i2c:inst4\|writeData_reg\[4\]\" with stuck data_in port to stuck value GND" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 699 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|I2C_FPGA\|i2c:inst4\|main_state 3 " "Info: State machine \"\|I2C_FPGA\|i2c:inst4\|main_state\" contains 3 states" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 39 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|I2C_FPGA\|i2c:inst4\|i2c_state 5 " "Info: State machine \"\|I2C_FPGA\|i2c:inst4\|i2c_state\" contains 5 states" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 40 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|I2C_FPGA\|i2c:inst4\|inner_state 11 " "Info: State machine \"\|I2C_FPGA\|i2c:inst4\|inner_state\" contains 11 states" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 41 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|I2C_FPGA\|i2c:inst4\|main_state " "Info: Selected Auto state machine encoding method for state machine \"\|I2C_FPGA\|i2c:inst4\|main_state\"" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 39 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|I2C_FPGA\|i2c:inst4\|main_state " "Info: Encoding result for state machine \"\|I2C_FPGA\|i2c:inst4\|main_state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "3 " "Info: Completed encoding using 3 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "i2c:inst4\|main_state.00 " "Info: Encoded state bit \"i2c:inst4\|main_state.00\"" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 39 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "i2c:inst4\|main_state.10 " "Info: Encoded state bit \"i2c:inst4\|main_state.10\"" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 39 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "i2c:inst4\|main_state.01 " "Info: Encoded state bit \"i2c:inst4\|main_state.01\"" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 39 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|I2C_FPGA\|i2c:inst4\|main_state.00 000 " "Info: State \"\|I2C_FPGA\|i2c:inst4\|main_state.00\" uses code string \"000\"" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 39 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|I2C_FPGA\|i2c:inst4\|main_state.01 101 " "Info: State \"\|I2C_FPGA\|i2c:inst4\|main_state.01\" uses code string \"101\"" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 39 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|I2C_FPGA\|i2c:inst4\|main_state.10 110 " "Info: State \"\|I2C_FPGA\|i2c:inst4\|main_state.10\" uses code string \"110\"" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 39 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0}  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 39 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|I2C_FPGA\|i2c:inst4\|i2c_state " "Info: Selected Auto state machine encoding method for state machine \"\|I2C_FPGA\|i2c:inst4\|i2c_state\"" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 40 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|I2C_FPGA\|i2c:inst4\|i2c_state " "Info: Encoding result for state machine \"\|I2C_FPGA\|i2c:inst4\|i2c_state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "5 " "Info: Completed encoding using 5 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "i2c:inst4\|i2c_state.read_data " "Info: Encoded state bit \"i2c:inst4\|i2c_state.read_data\"" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 40 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "i2c:inst4\|i2c_state.sendaddr " "Info: Encoded state bit \"i2c:inst4\|i2c_state.sendaddr\"" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 40 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "i2c:inst4\|i2c_state.write_data " "Info: Encoded state bit \"i2c:inst4\|i2c_state.write_data\"" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 40 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "i2c:inst4\|i2c_state.ini " "Info: Encoded state bit \"i2c:inst4\|i2c_state.ini\"" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 40 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "i2c:inst4\|i2c_state.read_ini " "Info: Encoded state bit \"i2c:inst4\|i2c_state.read_ini\"" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 40 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|I2C_FPGA\|i2c:inst4\|i2c_state.ini 00000 " "Info: State \"\|I2C_FPGA\|i2c:inst4\|i2c_state.ini\" uses code string \"00000\"" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 40 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|I2C_FPGA\|i2c:inst4\|i2c_state.read_ini 00011 " "Info: State \"\|I2C_FPGA\|i2c:inst4\|i2c_state.read_ini\" uses code string \"00011\"" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 40 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|I2C_FPGA\|i2c:inst4\|i2c_state.write_data 00110 " "Info: State \"\|I2C_FPGA\|i2c:inst4\|i2c_state.write_data\" uses code string \"00110\"" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 40 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|I2C_FPGA\|i2c:inst4\|i2c_state.sendaddr 01010 " "Info: State \"\|I2C_FPGA\|i2c:inst4\|i2c_state.sendaddr\" uses code string \"01010\"" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 40 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|I2C_FPGA\|i2c:inst4\|i2c_state.read_data 10010 " "Info: State \"\|I2C_FPGA\|i2c:inst4\|i2c_state.read_data\" uses code string \"10010\"" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 40 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0}  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 40 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|I2C_FPGA\|i2c:inst4\|inner_state " "Info: Selected Auto state machine encoding method for state machine \"\|I2C_FPGA\|i2c:inst4\|inner_state\"" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 41 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|I2C_FPGA\|i2c:inst4\|inner_state " "Info: Encoding result for state machine \"\|I2C_FPGA\|i2c:inst4\|inner_state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "11 " "Info: Completed encoding using 11 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "i2c:inst4\|inner_state.stop " "Info: Encoded state bit \"i2c:inst4\|inner_state.stop\"" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 41 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "i2c:inst4\|inner_state.first " "Info: Encoded state bit \"i2c:inst4\|inner_state.first\"" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 41 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "i2c:inst4\|inner_state.second " "Info: Encoded state bit \"i2c:inst4\|inner_state.second\"" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 41 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "i2c:inst4\|inner_state.third " "Info: Encoded state bit \"i2c:inst4\|inner_state.third\"" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 41 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "i2c:inst4\|inner_state.fourth " "Info: Encoded state bit \"i2c:inst4\|inner_state.fourth\"" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 41 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "i2c:inst4\|inner_state.fifth " "Info: Encoded state bit \"i2c:inst4\|inner_state.fifth\"" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 41 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "i2c:inst4\|inner_state.sixth " "Info: Encoded state bit \"i2c:inst4\|inner_state.sixth\"" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 41 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "i2c:inst4\|inner_state.seventh " "Info: Encoded state bit \"i2c:inst4\|inner_state.seventh\"" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 41 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "i2c:inst4\|inner_state.eighth " "Info: Encoded state bit \"i2c:inst4\|inner_state.eighth\"" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 41 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "i2c:inst4\|inner_state.ack " "Info: Encoded state bit \"i2c:inst4\|inner_state.ack\"" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 41 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "i2c:inst4\|inner_state.start " "Info: Encoded state bit \"i2c:inst4\|inner_state.start\"" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 41 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|I2C_FPGA\|i2c:inst4\|inner_state.start 00000000000 " "Info: State \"\|I2C_FPGA\|i2c:inst4\|inner_state.start\" uses code string \"00000000000\"" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 41 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|I2C_FPGA\|i2c:inst4\|inner_state.ack 00000000011 " "Info: State \"\|I2C_FPGA\|i2c:inst4\|inner_state.ack\" uses code string \"00000000011\"" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 41 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|I2C_FPGA\|i2c:inst4\|inner_state.eighth 00000000101 " "Info: State \"\|I2C_FPGA\|i2c:inst4\|inner_state.eighth\" uses code string \"00000000101\"" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 41 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|I2C_FPGA\|i2c:inst4\|inner_state.seventh 00000001001 " "Info: State \"\|I2C_FPGA\|i2c:inst4\|inner_state.seventh\" uses code string \"00000001001\"" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 41 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|I2C_FPGA\|i2c:inst4\|inner_state.sixth 00000010001 " "Info: State \"\|I2C_FPGA\|i2c:inst4\|inner_state.sixth\" uses code string \"00000010001\"" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 41 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|I2C_FPGA\|i2c:inst4\|inner_state.fifth 00000100001 " "Info: State \"\|I2C_FPGA\|i2c:inst4\|inner_state.fifth\" uses code string \"00000100001\"" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 41 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|I2C_FPGA\|i2c:inst4\|inner_state.fourth 00001000001 " "Info: State \"\|I2C_FPGA\|i2c:inst4\|inner_state.fourth\" uses code string \"00001000001\"" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 41 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|I2C_FPGA\|i2c:inst4\|inner_state.third 00010000001 " "Info: State \"\|I2C_FPGA\|i2c:inst4\|inner_state.third\" uses code string \"00010000001\"" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 41 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|I2C_FPGA\|i2c:inst4\|inner_state.second 00100000001 " "Info: State \"\|I2C_FPGA\|i2c:inst4\|inner_state.second\" uses code string \"00100000001\"" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 41 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|I2C_FPGA\|i2c:inst4\|inner_state.first 01000000001 " "Info: State \"\|I2C_FPGA\|i2c:inst4\|inner_state.first\" uses code string \"01000000001\"" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 41 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|I2C_FPGA\|i2c:inst4\|inner_state.stop 10000000001 " "Info: State \"\|I2C_FPGA\|i2c:inst4\|inner_state.stop\" uses code string \"10000000001\"" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 41 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0}  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 41 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "i2c:inst4\|seg_data\[6\] " "Warning: Latch i2c:inst4\|seg_data\[6\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA i2c:inst4\|en\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal i2c:inst4\|en\[1\]" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 716 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 732 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "i2c:inst4\|seg_data\[5\] " "Warning: Latch i2c:inst4\|seg_data\[5\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA i2c:inst4\|en\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal i2c:inst4\|en\[1\]" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 716 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 732 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "i2c:inst4\|seg_data\[4\] " "Warning: Latch i2c:inst4\|seg_data\[4\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA i2c:inst4\|en\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal i2c:inst4\|en\[1\]" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 716 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 732 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "i2c:inst4\|seg_data\[3\] " "Warning: Latch i2c:inst4\|seg_data\[3\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA i2c:inst4\|en\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal i2c:inst4\|en\[1\]" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 716 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 732 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "i2c:inst4\|seg_data\[2\] " "Warning: Latch i2c:inst4\|seg_data\[2\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA i2c:inst4\|en\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal i2c:inst4\|en\[1\]" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 716 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 732 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "i2c:inst4\|seg_data\[1\] " "Warning: Latch i2c:inst4\|seg_data\[1\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA i2c:inst4\|en\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal i2c:inst4\|en\[1\]" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 716 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 732 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "i2c:inst4\|seg_data\[0\] " "Warning: Latch i2c:inst4\|seg_data\[0\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA i2c:inst4\|en\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal i2c:inst4\|en\[1\]" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 716 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 732 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "seg7\[7\] VCC " "Warning: Pin \"seg7\[7\]\" stuck at VCC" {  } { { "I2C_FPGA.bdf" "" { Schematic "D:/I2C_CPLD/I2C_FPGA.bdf" { { 32 848 1024 48 "seg7\[7..0\]" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "333 " "Info: Implemented 333 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "4 " "Info: Implemented 4 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "11 " "Info: Implemented 11 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_BIDIRS" "1 " "Info: Implemented 1 bidirectional pins" {  } {  } 0 0 "Implemented %1!d! bidirectional pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "317 " "Info: Implemented 317 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 43 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 43 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 20 15:37:56 2006 " "Info: Processing ended: Mon Nov 20 15:37:56 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:35 " "Info: Elapsed time: 00:00:35" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}