i2c_fpga.map.qmsg

Verilog 经典实例

{ "Warning" "WVRFX_VERI_INCOMPLETE_CASE_STATEMENT" "i2c.v(381) " "Warning (10270): Verilog HDL statement warning at i2c.v(381): incomplete Case Statement has no default case item" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 381 0 0 } }  } 0 10270 "Verilog HDL statement warning at %1!s!: incomplete Case Statement has no default case item" 0 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "i2c.v(381) " "Info (10264): Verilog HDL Case Statement information at i2c.v(381): all case item expressions in this case statement are onehot" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 381 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 12 i2c.v(712) " "Warning (10230): Verilog HDL assignment warning at i2c.v(712): truncated value with size 32 to match size of target (12)" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 712 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "i2c.v(720) " "Info (10264): Verilog HDL Case Statement information at i2c.v(720): all case item expressions in this case statement are onehot" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 720 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_CASE_STATEMENT" "i2c.v(732) " "Warning (10270): Verilog HDL statement warning at i2c.v(732): incomplete Case Statement has no default case item" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 732 0 0 } }  } 0 10270 "Verilog HDL statement warning at %1!s!: incomplete Case Statement has no default case item" 0 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "seg_data i2c.v(730) " "Warning (10240): Verilog HDL Always Construct warning at i2c.v(730): variable \"seg_data\" may not be assigned a new value in every possible path through the Always Construct.  Variable \"seg_data\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 730 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" may not be assigned a new value in every possible path through the Always Construct.  Variable \"%1!s!\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "i2c_test i2c_test:inst1 " "Info: Elaborating entity \"i2c_test\" for hierarchy \"i2c_test:inst1\"" {  } { { "I2C_FPGA.bdf" "inst1" { Schematic "D:/I2C_CPLD/I2C_FPGA.bdf" { { -8 392 552 88 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "clk i2c_test.v(3) " "Info (10035): Verilog HDL or VHDL information at i2c_test.v(3): object \"clk\" declared but not used" {  } { { "i2c_test.v" "" { Text "D:/I2C_CPLD/i2c_test.v" 3 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "delay_reset_block.bdf 1 1 " "Warning: Using design file delay_reset_block.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 delay_reset_block " "Info: Found entity 1: delay_reset_block" {  } { { "delay_reset_block.bdf" "" { Schematic "D:/I2C_CPLD/delay_reset_block.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "delay_reset_block delay_reset_block:inst2 " "Info: Elaborating entity \"delay_reset_block\" for hierarchy \"delay_reset_block:inst2\"" {  } { { "I2C_FPGA.bdf" "inst2" { Schematic "D:/I2C_CPLD/I2C_FPGA.bdf" { { 8 152 344 104 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "reset_counter.v 1 1 " "Warning: Using design file reset_counter.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 reset_counter " "Info: Found entity 1: reset_counter" {  } { { "reset_counter.v" "" { Text "D:/I2C_CPLD/reset_counter.v" 36 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reset_counter delay_reset_block:inst2\|reset_counter:inst " "Info: Elaborating entity \"reset_counter\" for hierarchy \"delay_reset_block:inst2\|reset_counter:inst\"" {  } { { "delay_reset_block.bdf" "inst" { Schematic "D:/I2C_CPLD/delay_reset_block.bdf" { { 224 688 832 336 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../altera/quartus51/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../altera/quartus51/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 233 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_counter delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component " "Info: Elaborating entity \"lpm_counter\" for hierarchy \"delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\"" {  } { { "reset_counter.v" "lpm_counter_component" { Text "D:/I2C_CPLD/reset_counter.v" 54 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_1ub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_1ub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_1ub " "Info: Found entity 1: cntr_1ub" {  } { { "db/cntr_1ub.tdf" "" { Text "D:/I2C_CPLD/db/cntr_1ub.tdf" 25 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_1ub delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated " "Info: Elaborating entity \"cntr_1ub\" for hierarchy \"delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\"" {  } { { "lpm_counter.tdf" "auto_generated" { Text "d:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 257 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "i2c:inst4\|addr\[7\] data_in GND " "Warning: Reduced register \"i2c:inst4\|addr\[7\]\" with stuck data_in port to stuck value GND" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 699 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "i2c:inst4\|addr\[6\] data_in GND " "Warning: Reduced register \"i2c:inst4\|addr\[6\]\" with stuck data_in port to stuck value GND" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 699 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "i2c:inst4\|addr\[5\] data_in GND " "Warning: Reduced register \"i2c:inst4\|addr\[5\]\" with stuck data_in port to stuck value GND" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 699 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "i2c:inst4\|addr\[4\] data_in GND " "Warning: Reduced register \"i2c:inst4\|addr\[4\]\" with stuck data_in port to stuck value GND" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 699 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "i2c:inst4\|addr\[3\] High " "Info: Power-up level of register \"i2c:inst4\|addr\[3\]\" is not specified -- using power-up level of High to minimize register" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 699 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "i2c:inst4\|addr\[3\] data_in VCC " "Warning: Reduced register \"i2c:inst4\|addr\[3\]\" with stuck data_in port to stuck value VCC" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 699 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "i2c:inst4\|addr\[2\] data_in GND " "Warning: Reduced register \"i2c:inst4\|addr\[2\]\" with stuck data_in port to stuck value GND" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 699 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "i2c:inst4\|addr\[1\] High " "Info: Power-up level of register \"i2c:inst4\|addr\[1\]\" is not specified -- using power-up level of High to minimize register" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 699 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "i2c:inst4\|addr\[1\] data_in VCC " "Warning: Reduced register \"i2c:inst4\|addr\[1\]\" with stuck data_in port to stuck value VCC" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 699 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}