i2c_fpga.hier_info

Verilog 经典实例

|I2C_FPGA
scl <= i2c:inst4.scl
clk => i2c:inst4.clk
clk => delay_reset_block:inst2.clock_in
clk => delay_reset_block:inst3.clock_in
reset => i2c:inst4.rst
reset => i2c_test:inst1.rst
write => delay_reset_block:inst2.reset_n
rd => delay_reset_block:inst3.reset_n
sda <= i2c:inst4.sda
seg7[0] <= i2c:inst4.seg_data[0]
seg7[1] <= i2c:inst4.seg_data[1]
seg7[2] <= i2c:inst4.seg_data[2]
seg7[3] <= i2c:inst4.seg_data[3]
seg7[4] <= i2c:inst4.seg_data[4]
seg7[5] <= i2c:inst4.seg_data[5]
seg7[6] <= i2c:inst4.seg_data[6]
seg7[7] <= i2c:inst4.seg_data[7]
segcom[0] <= i2c:inst4.en[0]
segcom[1] <= i2c:inst4.en[1]


|I2C_FPGA|i2c:inst4
clk => cnt_delay[18].CLK
clk => cnt_delay[17].CLK
clk => cnt_delay[16].CLK
clk => cnt_delay[15].CLK
clk => cnt_delay[14].CLK
clk => cnt_delay[13].CLK
clk => cnt_delay[12].CLK
clk => cnt_delay[11].CLK
clk => cnt_delay[10].CLK
clk => cnt_delay[9].CLK
clk => cnt_delay[8].CLK
clk => cnt_delay[7].CLK
clk => cnt_delay[6].CLK
clk => cnt_delay[5].CLK
clk => cnt_delay[4].CLK
clk => cnt_delay[3].CLK
clk => cnt_delay[2].CLK
clk => cnt_delay[1].CLK
clk => cnt_delay[0].CLK
clk => clk_div[7].CLK
clk => clk_div[6].CLK
clk => clk_div[5].CLK
clk => clk_div[4].CLK
clk => clk_div[3].CLK
clk => clk_div[2].CLK
clk => clk_div[1].CLK
clk => clk_div[0].CLK
clk => phase0.CLK
clk => phase1.CLK
clk => phase2.CLK
clk => phase3.CLK
clk => start_delaycnt.CLK
clk => scl~reg0.CLK
clk => sda_buf.CLK
clk => link.CLK
clk => writeData_reg[7].CLK
clk => writeData_reg[6].CLK
clk => writeData_reg[5].CLK
clk => writeData_reg[4].CLK
clk => writeData_reg[3].CLK
clk => writeData_reg[2].CLK
clk => writeData_reg[1].CLK
clk => writeData_reg[0].CLK
clk => readData_reg[7].CLK
clk => readData_reg[6].CLK
clk => readData_reg[5].CLK
clk => readData_reg[4].CLK
clk => readData_reg[3].CLK
clk => readData_reg[2].CLK
clk => readData_reg[1].CLK
clk => readData_reg[0].CLK
clk => addr[7].CLK
clk => addr[6].CLK
clk => addr[5].CLK
clk => addr[4].CLK
clk => addr[3].CLK
clk => addr[2].CLK
clk => addr[1].CLK
clk => addr[0].CLK
clk => cnt_scan[11].CLK
clk => cnt_scan[10].CLK
clk => cnt_scan[9].CLK
clk => cnt_scan[8].CLK
clk => cnt_scan[7].CLK
clk => cnt_scan[6].CLK
clk => cnt_scan[5].CLK
clk => cnt_scan[4].CLK
clk => cnt_scan[3].CLK
clk => cnt_scan[2].CLK
clk => cnt_scan[1].CLK
clk => cnt_scan[0].CLK
clk => en[1]~reg0.CLK
clk => en[0]~reg0.CLK
clk => cnt_delay[19].CLK
clk => main_state~30.IN1
clk => i2c_state~25.IN1
clk => inner_state~57.IN1
rst => start_delaycnt~3.OUTPUTSELECT
rst => main_state~27.OUTPUTSELECT
rst => main_state~28.OUTPUTSELECT
rst => main_state~29.OUTPUTSELECT
rst => i2c_state~20.OUTPUTSELECT
rst => i2c_state~21.OUTPUTSELECT
rst => i2c_state~22.OUTPUTSELECT
rst => i2c_state~23.OUTPUTSELECT
rst => i2c_state~24.OUTPUTSELECT
rst => inner_state~46.OUTPUTSELECT
rst => inner_state~47.OUTPUTSELECT
rst => inner_state~48.OUTPUTSELECT
rst => inner_state~49.OUTPUTSELECT
rst => inner_state~50.OUTPUTSELECT
rst => inner_state~51.OUTPUTSELECT
rst => inner_state~52.OUTPUTSELECT
rst => inner_state~53.OUTPUTSELECT
rst => inner_state~54.OUTPUTSELECT
rst => inner_state~55.OUTPUTSELECT
rst => inner_state~56.OUTPUTSELECT
rst => scl~2.OUTPUTSELECT
rst => sda_buf~28.OUTPUTSELECT
rst => link~6.OUTPUTSELECT
rst => writeData_reg~8.OUTPUTSELECT
rst => writeData_reg~9.OUTPUTSELECT
rst => writeData_reg~10.OUTPUTSELECT
rst => writeData_reg~11.OUTPUTSELECT
rst => writeData_reg~12.OUTPUTSELECT
rst => writeData_reg~13.OUTPUTSELECT
rst => writeData_reg~14.OUTPUTSELECT
rst => writeData_reg~15.OUTPUTSELECT
rst => readData_reg~24.OUTPUTSELECT
rst => readData_reg~25.OUTPUTSELECT
rst => readData_reg~26.OUTPUTSELECT
rst => readData_reg~27.OUTPUTSELECT
rst => readData_reg~28.OUTPUTSELECT
rst => readData_reg~29.OUTPUTSELECT
rst => readData_reg~30.OUTPUTSELECT
rst => readData_reg~31.OUTPUTSELECT
rst => cnt_scan~0.OUTPUTSELECT
rst => cnt_scan~1.OUTPUTSELECT
rst => cnt_scan~2.OUTPUTSELECT
rst => cnt_scan~3.OUTPUTSELECT
rst => cnt_scan~4.OUTPUTSELECT
rst => cnt_scan~5.OUTPUTSELECT
rst => cnt_scan~6.OUTPUTSELECT
rst => cnt_scan~7.OUTPUTSELECT
rst => cnt_scan~8.OUTPUTSELECT
rst => cnt_scan~9.OUTPUTSELECT
rst => cnt_scan~10.OUTPUTSELECT
rst => cnt_scan~11.OUTPUTSELECT
rst => en~2.OUTPUTSELECT
rst => en~3.OUTPUTSELECT
rst => cnt_delay~40.OUTPUTSELECT
rst => cnt_delay~41.OUTPUTSELECT
rst => cnt_delay~42.OUTPUTSELECT
rst => cnt_delay~43.OUTPUTSELECT
rst => cnt_delay~44.OUTPUTSELECT
rst => cnt_delay~45.OUTPUTSELECT
rst => cnt_delay~46.OUTPUTSELECT
rst => cnt_delay~47.OUTPUTSELECT
rst => cnt_delay~48.OUTPUTSELECT
rst => cnt_delay~49.OUTPUTSELECT
rst => cnt_delay~50.OUTPUTSELECT
rst => cnt_delay~51.OUTPUTSELECT
rst => cnt_delay~52.OUTPUTSELECT
rst => cnt_delay~53.OUTPUTSELECT
rst => cnt_delay~54.OUTPUTSELECT
rst => cnt_delay~55.OUTPUTSELECT
rst => cnt_delay~56.OUTPUTSELECT
rst => cnt_delay~57.OUTPUTSELECT
rst => cnt_delay~58.OUTPUTSELECT
rst => cnt_delay~59.OUTPUTSELECT
rst => clk_div~8.OUTPUTSELECT
rst => clk_div~9.OUTPUTSELECT
rst => clk_div~10.OUTPUTSELECT
rst => clk_div~11.OUTPUTSELECT
rst => clk_div~12.OUTPUTSELECT
rst => clk_div~13.OUTPUTSELECT
rst => clk_div~14.OUTPUTSELECT
rst => clk_div~15.OUTPUTSELECT
rst => phase0~2.OUTPUTSELECT
rst => phase1~2.OUTPUTSELECT
rst => phase2~2.OUTPUTSELECT
rst => phase3~2.OUTPUTSELECT
rst => addr[7].ENA
rst => addr[6].ENA
rst => addr[5].ENA
rst => addr[4].ENA
rst => addr[3].ENA
rst => addr[2].ENA
rst => addr[1].ENA
rst => addr[0].ENA
data_in[0] => writeData_reg~7.DATAB
data_in[1] => writeData_reg~6.DATAB
data_in[2] => writeData_reg~5.DATAB
data_in[3] => writeData_reg~4.DATAB
scl <= scl~reg0.DB_MAX_OUTPUT_PORT_TYPE
sda <= sda~0
wr_input => main_state~3.OUTPUTSELECT
wr_input => main_state~4.OUTPUTSELECT
wr_input => main_state~5.OUTPUTSELECT
wr_input => always2~0.IN1
rd_input => main_state~0.OUTPUTSELECT
rd_input => main_state~1.OUTPUTSELECT
rd_input => main_state~2.OUTPUTSELECT
rd_input => always2~0.IN0
en[0] <= en[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
en[1] <= en[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
seg_data[0] <= seg_data[0]$latch.DB_MAX_OUTPUT_PORT_TYPE
seg_data[1] <= seg_data[1]$latch.DB_MAX_OUTPUT_PORT_TYPE
seg_data[2] <= seg_data[2]$latch.DB_MAX_OUTPUT_PORT_TYPE
seg_data[3] <= seg_data[3]$latch.DB_MAX_OUTPUT_PORT_TYPE
seg_data[4] <= seg_data[4]$latch.DB_MAX_OUTPUT_PORT_TYPE
seg_data[5] <= seg_data[5]$latch.DB_MAX_OUTPUT_PORT_TYPE
seg_data[6] <= seg_data[6]$latch.DB_MAX_OUTPUT_PORT_TYPE
seg_data[7] <= <VCC>


|I2C_FPGA|i2c_test:inst1
clk => ~NO_FANOUT~
rst => counter[2].ACLR
rst => counter[1].ACLR
rst => counter[0].ACLR
rst => counter[3].ACLR
data_out[0] <= counter[0].DB_MAX_OUTPUT_PORT_TYPE
data_out[1] <= counter[1].DB_MAX_OUTPUT_PORT_TYPE
data_out[2] <= counter[2].DB_MAX_OUTPUT_PORT_TYPE
data_out[3] <= counter[3].DB_MAX_OUTPUT_PORT_TYPE
wr_input => wr_output.DATAIN
wr_input => counter[2].CLK
wr_input => counter[1].CLK
wr_input => counter[0].CLK
wr_input => counter[3].CLK
rd_input => rd_output.DATAIN
wr_output <= wr_input.DB_MAX_OUTPUT_PORT_TYPE
rd_output <= rd_input.DB_MAX_OUTPUT_PORT_TYPE


|I2C_FPGA|delay_reset_block:inst2
delayed_reset_n <= inst4.DB_MAX_OUTPUT_PORT_TYPE
reset_n => inst4.IN0
reset_n => inst5.IN0
clock_in => reset_counter:inst.clock


|I2C_FPGA|delay_reset_block:inst2|reset_counter:inst
clock => clock~0.IN1
cnt_en => cnt_en~0.IN1
aclr => aclr~0.IN1
q[0] <= lpm_counter:lpm_counter_component.q
q[1] <= lpm_counter:lpm_counter_component.q
q[2] <= lpm_counter:lpm_counter_component.q
q[3] <= lpm_counter:lpm_counter_component.q
q[4] <= lpm_counter:lpm_counter_component.q
q[5] <= lpm_counter:lpm_counter_component.q
q[6] <= lpm_counter:lpm_counter_component.q
q[7] <= lpm_counter:lpm_counter_component.q
q[8] <= lpm_counter:lpm_counter_component.q
q[9] <= lpm_counter:lpm_counter_component.q
cout <= lpm_counter:lpm_counter_component.cout


|I2C_FPGA|delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component
clock => cntr_1ub:auto_generated.clock
clk_en => ~NO_FANOUT~
cnt_en => cntr_1ub:auto_generated.cnt_en
updown => ~NO_FANOUT~
aclr => cntr_1ub:auto_generated.aclr
aset => ~NO_FANOUT~
aconst => ~NO_FANOUT~
aload => ~NO_FANOUT~
sclr => ~NO_FANOUT~
sset => ~NO_FANOUT~
sconst => ~NO_FANOUT~
sload => ~NO_FANOUT~
data[0] => ~NO_FANOUT~
data[1] => ~NO_FANOUT~
data[2] => ~NO_FANOUT~
data[3] => ~NO_FANOUT~
data[4] => ~NO_FANOUT~
data[5] => ~NO_FANOUT~
data[6] => ~NO_FANOUT~
data[7] => ~NO_FANOUT~
data[8] => ~NO_FANOUT~
data[9] => ~NO_FANOUT~
cin => ~NO_FANOUT~
q[0] <= cntr_1ub:auto_generated.q[0]
q[1] <= cntr_1ub:auto_generated.q[1]
q[2] <= cntr_1ub:auto_generated.q[2]
q[3] <= cntr_1ub:auto_generated.q[3]
q[4] <= cntr_1ub:auto_generated.q[4]
q[5] <= cntr_1ub:auto_generated.q[5]
q[6] <= cntr_1ub:auto_generated.q[6]
q[7] <= cntr_1ub:auto_generated.q[7]
q[8] <= cntr_1ub:auto_generated.q[8]
q[9] <= cntr_1ub:auto_generated.q[9]
cout <= cntr_1ub:auto_generated.cout
eq[0] <= <GND>
eq[1] <= <GND>
eq[2] <= <GND>
eq[3] <= <GND>
eq[4] <= <GND>
eq[5] <= <GND>
eq[6] <= <GND>
eq[7] <= <GND>
eq[8] <= <GND>
eq[9] <= <GND>
eq[10] <= <GND>
eq[11] <= <GND>
eq[12] <= <GND>
eq[13] <= <GND>
eq[14] <= <GND>
eq[15] <= <GND>


|I2C_FPGA|delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated
aclr => counter_cella0.ACLR
aclr => counter_cella1.ACLR
aclr => counter_cella2.ACLR
aclr => counter_cella3.ACLR
aclr => counter_cella4.ACLR
aclr => counter_cella5.ACLR
aclr => counter_cella6.ACLR
aclr => counter_cella7.ACLR
aclr => counter_cella8.ACLR
aclr => counter_cella9.ACLR
clock => counter_cella0.CLK
clock => counter_cella1.CLK
clock => counter_cella2.CLK
clock => counter_cella3.CLK
clock => counter_cella4.CLK
clock => counter_cella5.CLK
clock => counter_cella6.CLK
clock => counter_cella7.CLK
clock => counter_cella8.CLK
clock => counter_cella9.CLK
cnt_en => counter_cella0.DATAB
cnt_en => counter_cella1.DATAB
cnt_en => counter_cella2.DATAB
cnt_en => counter_cella3.DATAB
cnt_en => counter_cella4.DATAB
cnt_en => counter_cella5.DATAB
cnt_en => counter_cella6.DATAB
cnt_en => counter_cella7.DATAB
cnt_en => counter_cella8.DATAB
cnt_en => counter_cella9.DATAB
cout <= cout_bit.COMBOUT
q[0] <= counter_cella0.REGOUT
q[1] <= counter_cella1.REGOUT
q[2] <= counter_cella2.REGOUT
q[3] <= counter_cella3.REGOUT
q[4] <= counter_cella4.REGOUT
q[5] <= counter_cella5.REGOUT
q[6] <= counter_cella6.REGOUT
q[7] <= counter_cella7.REGOUT
q[8] <= counter_cella8.REGOUT
q[9] <= counter_cella9.REGOUT


|I2C_FPGA|delay_reset_block:inst3
delayed_reset_n <= inst4.DB_MAX_OUTPUT_PORT_TYPE
reset_n => inst4.IN0
reset_n => inst5.IN0
clock_in => reset_counter:inst.clock


|I2C_FPGA|delay_reset_block:inst3|reset_counter:inst
clock => clock~0.IN1
cnt_en => cnt_en~0.IN1
aclr => aclr~0.IN1
q[0] <= lpm_counter:lpm_counter_component.q
q[1] <= lpm_counter:lpm_counter_component.q
q[2] <= lpm_counter:lpm_counter_component.q
q[3] <= lpm_counter:lpm_counter_component.q
q[4] <= lpm_counter:lpm_counter_component.q
q[5] <= lpm_counter:lpm_counter_component.q
q[6] <= lpm_counter:lpm_counter_component.q
q[7] <= lpm_counter:lpm_counter_component.q
q[8] <= lpm_counter:lpm_counter_component.q
q[9] <= lpm_counter:lpm_counter_component.q
cout <= lpm_counter:lpm_counter_component.cout


|I2C_FPGA|delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component
clock => cntr_1ub:auto_generated.clock
clk_en => ~NO_FANOUT~
cnt_en => cntr_1ub:auto_generated.cnt_en
updown => ~NO_FANOUT~
aclr => cntr_1ub:auto_generated.aclr
aset => ~NO_FANOUT~
aconst => ~NO_FANOUT~
aload => ~NO_FANOUT~
sclr => ~NO_FANOUT~
sset => ~NO_FANOUT~
sconst => ~NO_FANOUT~
sload => ~NO_FANOUT~
data[0] => ~NO_FANOUT~
data[1] => ~NO_FANOUT~
data[2] => ~NO_FANOUT~
data[3] => ~NO_FANOUT~
data[4] => ~NO_FANOUT~
data[5] => ~NO_FANOUT~
data[6] => ~NO_FANOUT~
data[7] => ~NO_FANOUT~
data[8] => ~NO_FANOUT~
data[9] => ~NO_FANOUT~
cin => ~NO_FANOUT~
q[0] <= cntr_1ub:auto_generated.q[0]
q[1] <= cntr_1ub:auto_generated.q[1]
q[2] <= cntr_1ub:auto_generated.q[2]
q[3] <= cntr_1ub:auto_generated.q[3]
q[4] <= cntr_1ub:auto_generated.q[4]
q[5] <= cntr_1ub:auto_generated.q[5]
q[6] <= cntr_1ub:auto_generated.q[6]
q[7] <= cntr_1ub:auto_generated.q[7]
q[8] <= cntr_1ub:auto_generated.q[8]
q[9] <= cntr_1ub:auto_generated.q[9]
cout <= cntr_1ub:auto_generated.cout
eq[0] <= <GND>
eq[1] <= <GND>
eq[2] <= <GND>
eq[3] <= <GND>
eq[4] <= <GND>
eq[5] <= <GND>
eq[6] <= <GND>
eq[7] <= <GND>
eq[8] <= <GND>
eq[9] <= <GND>
eq[10] <= <GND>
eq[11] <= <GND>
eq[12] <= <GND>
eq[13] <= <GND>
eq[14] <= <GND>
eq[15] <= <GND>


|I2C_FPGA|delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated
aclr => counter_cella0.ACLR
aclr => counter_cella1.ACLR
aclr => counter_cella2.ACLR
aclr => counter_cella3.ACLR
aclr => counter_cella4.ACLR
aclr => counter_cella5.ACLR
aclr => counter_cella6.ACLR
aclr => counter_cella7.ACLR
aclr => counter_cella8.ACLR
aclr => counter_cella9.ACLR
clock => counter_cella0.CLK
clock => counter_cella1.CLK
clock => counter_cella2.CLK
clock => counter_cella3.CLK
clock => counter_cella4.CLK
clock => counter_cella5.CLK
clock => counter_cella6.CLK
clock => counter_cella7.CLK
clock => counter_cella8.CLK
clock => counter_cella9.CLK
cnt_en => counter_cella0.DATAB
cnt_en => counter_cella1.DATAB
cnt_en => counter_cella2.DATAB
cnt_en => counter_cella3.DATAB
cnt_en => counter_cella4.DATAB
cnt_en => counter_cella5.DATAB
cnt_en => counter_cella6.DATAB
cnt_en => counter_cella7.DATAB
cnt_en => counter_cella8.DATAB
cnt_en => counter_cella9.DATAB
cout <= cout_bit.COMBOUT
q[0] <= counter_cella0.REGOUT
q[1] <= counter_cella1.REGOUT
q[2] <= counter_cella2.REGOUT
q[3] <= counter_cella3.REGOUT
q[4] <= counter_cella4.REGOUT
q[5] <= counter_cella5.REGOUT
q[6] <= counter_cella6.REGOUT
q[7] <= counter_cella7.REGOUT
q[8] <= counter_cella8.REGOUT
q[9] <= counter_cella9.REGOUT