i2c_fpga.tan.qmsg

Verilog 经典实例

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register i2c_test:inst1\|counter\[0\] register i2c:inst4\|writeData_reg\[0\] 79.99 MHz 12.501 ns Internal " "Info: Clock \"clk\" has Internal fmax of 79.99 MHz between source register \"i2c_test:inst1\|counter\[0\]\" and destination register \"i2c:inst4\|writeData_reg\[0\]\" (period= 12.501 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.832 ns + Longest register register " "Info: + Longest register to register delay is 1.832 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns i2c_test:inst1\|counter\[0\] 1 REG LC_X11_Y8_N4 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X11_Y8_N4; Fanout = 5; REG Node = 'i2c_test:inst1\|counter\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "I2C_FPGA" "UNKNOWN" "V1" "D:/I2C_CPLD/db/I2C_FPGA.quartus_db" { Floorplan "D:/I2C_CPLD/" "" "" { i2c_test:inst1|counter[0] } "NODE_NAME" } "" } } { "i2c_test.v" "" { Text "D:/I2C_CPLD/i2c_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.028 ns) + CELL(0.804 ns) 1.832 ns i2c:inst4\|writeData_reg\[0\] 2 REG LC_X11_Y8_N7 2 " "Info: 2: + IC(1.028 ns) + CELL(0.804 ns) = 1.832 ns; Loc. = LC_X11_Y8_N7; Fanout = 2; REG Node = 'i2c:inst4\|writeData_reg\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "I2C_FPGA" "UNKNOWN" "V1" "D:/I2C_CPLD/db/I2C_FPGA.quartus_db" { Floorplan "D:/I2C_CPLD/" "" "1.832 ns" { i2c_test:inst1|counter[0] i2c:inst4|writeData_reg[0] } "NODE_NAME" } "" } } { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 699 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.804 ns ( 43.89 % ) " "Info: Total cell delay = 0.804 ns ( 43.89 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.028 ns ( 56.11 % ) " "Info: Total interconnect delay = 1.028 ns ( 56.11 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "I2C_FPGA" "UNKNOWN" "V1" "D:/I2C_CPLD/db/I2C_FPGA.quartus_db" { Floorplan "D:/I2C_CPLD/" "" "1.832 ns" { i2c_test:inst1|counter[0] i2c:inst4|writeData_reg[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "1.832 ns" { i2c_test:inst1|counter[0] i2c:inst4|writeData_reg[0] } { 0.000ns 1.028ns } { 0.000ns 0.804ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-9.960 ns - Smallest " "Info: - Smallest clock skew is -9.960 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.819 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 101 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 101; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "I2C_FPGA" "UNKNOWN" "V1" "D:/I2C_CPLD/db/I2C_FPGA.quartus_db" { Floorplan "D:/I2C_CPLD/" "" "" { clk } "NODE_NAME" } "" } } { "I2C_FPGA.bdf" "" { Schematic "D:/I2C_CPLD/I2C_FPGA.bdf" { { -96 -104 64 -80 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(0.918 ns) 3.819 ns i2c:inst4\|writeData_reg\[0\] 2 REG LC_X11_Y8_N7 2 " "Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X11_Y8_N7; Fanout = 2; REG Node = 'i2c:inst4\|writeData_reg\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "I2C_FPGA" "UNKNOWN" "V1" "D:/I2C_CPLD/db/I2C_FPGA.quartus_db" { Floorplan "D:/I2C_CPLD/" "" "2.656 ns" { clk i2c:inst4|writeData_reg[0] } "NODE_NAME" } "" } } { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 699 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 54.49 % ) " "Info: Total cell delay = 2.081 ns ( 54.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.738 ns ( 45.51 % ) " "Info: Total interconnect delay = 1.738 ns ( 45.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "I2C_FPGA" "UNKNOWN" "V1" "D:/I2C_CPLD/db/I2C_FPGA.quartus_db" { Floorplan "D:/I2C_CPLD/" "" "3.819 ns" { clk i2c:inst4|writeData_reg[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout i2c:inst4|writeData_reg[0] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 13.779 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 13.779 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 101 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 101; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "I2C_FPGA" "UNKNOWN" "V1" "D:/I2C_CPLD/db/I2C_FPGA.quartus_db" { Floorplan "D:/I2C_CPLD/" "" "" { clk } "NODE_NAME" } "" } } { "I2C_FPGA.bdf" "" { Schematic "D:/I2C_CPLD/I2C_FPGA.bdf" { { -96 -104 64 -80 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|safe_q\[0\] 2 REG LC_X13_Y6_N5 3 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X13_Y6_N5; Fanout = 3; REG Node = 'delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|safe_q\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "I2C_FPGA" "UNKNOWN" "V1" "D:/I2C_CPLD/db/I2C_FPGA.quartus_db" { Floorplan "D:/I2C_CPLD/" "" "3.032 ns" { clk delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|safe_q[0] } "NODE_NAME" } "" } } { "db/cntr_1ub.tdf" "" { Text "D:/I2C_CPLD/db/cntr_1ub.tdf" 125 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.883 ns) + CELL(0.978 ns) 6.056 ns delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|counter_cella0~COUT 3 COMB LC_X13_Y6_N5 2 " "Info: 3: + IC(0.883 ns) + CELL(0.978 ns) = 6.056 ns; Loc. = LC_X13_Y6_N5; Fanout = 2; COMB Node = 'delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|counter_cella0~COUT'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "I2C_FPGA" "UNKNOWN" "V1" "D:/I2C_CPLD/db/I2C_FPGA.quartus_db" { Floorplan "D:/I2C_CPLD/" "" "1.861 ns" { delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|safe_q[0] delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|counter_cella0~COUT } "NODE_NAME" } "" } } { "db/cntr_1ub.tdf" "" { Text "D:/I2C_CPLD/db/cntr_1ub.tdf" 34 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 6.179 ns delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|counter_cella1~COUT 4 COMB LC_X13_Y6_N6 2 " "Info: 4: + IC(0.000 ns) + CELL(0.123 ns) = 6.179 ns; Loc. = LC_X13_Y6_N6; Fanout = 2; COMB Node = 'delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|counter_cella1~COUT'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "I2C_FPGA" "UNKNOWN" "V1" "D:/I2C_CPLD/db/I2C_FPGA.quartus_db" { Floorplan "D:/I2C_CPLD/" "" "0.123 ns" { delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|counter_cella0~COUT delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|counter_cella1~COUT } "NODE_NAME" } "" } } { "db/cntr_1ub.tdf" "" { Text "D:/I2C_CPLD/db/cntr_1ub.tdf" 41 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 6.302 ns delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|counter_cella2~COUT 5 COMB LC_X13_Y6_N7 2 " "Info: 5: + IC(0.000 ns) + CELL(0.123 ns) = 6.302 ns; Loc. = LC_X13_Y6_N7; Fanout = 2; COMB Node = 'delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|counter_cella2~COUT'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "I2C_FPGA" "UNKNOWN" "V1" "D:/I2C_CPLD/db/I2C_FPGA.quartus_db" { Floorplan "D:/I2C_CPLD/" "" "0.123 ns" { delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|counter_cella1~COUT delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|counter_cella2~COUT } "NODE_NAME" } "" } } { "db/cntr_1ub.tdf" "" { Text "D:/I2C_CPLD/db/cntr_1ub.tdf" 49 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 6.425 ns delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|counter_cella3~COUT 6 COMB LC_X13_Y6_N8 2 " "Info: 6: + IC(0.000 ns) + CELL(0.123 ns) = 6.425 ns; Loc. = LC_X13_Y6_N8; Fanout = 2; COMB Node = 'delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|counter_cella3~COUT'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "I2C_FPGA" "UNKNOWN" "V1" "D:/I2C_CPLD/db/I2C_FPGA.quartus_db" { Floorplan "D:/I2C_CPLD/" "" "0.123 ns" { delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|counter_cella2~COUT delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|counter_cella3~COUT } "NODE_NAME" } "" } } { "db/cntr_1ub.tdf" "" { Text "D:/I2C_CPLD/db/cntr_1ub.tdf" 57 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.399 ns) 6.824 ns delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|counter_cella4~COUT 7 COMB LC_X13_Y6_N9 6 " "Info: 7: + IC(0.000 ns) + CELL(0.399 ns) = 6.824 ns; Loc. = LC_X13_Y6_N9; Fanout = 6; COMB Node = 'delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|counter_cella4~COUT'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "I2C_FPGA" "UNKNOWN" "V1" "D:/I2C_CPLD/db/I2C_FPGA.quartus_db" { Floorplan "D:/I2C_CPLD/" "" "0.399 ns" { delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|counter_cella3~COUT delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|counter_cella4~COUT } "NODE_NAME" } "" } } { "db/cntr_1ub.tdf" "" { Text "D:/I2C_CPLD/db/cntr_1ub.tdf" 65 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.246 ns) 7.070 ns delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|counter_cella9~COUT 8 COMB LC_X14_Y6_N4 1 " "Info: 8: + IC(0.000 ns) + CELL(0.246 ns) = 7.070 ns; Loc. = LC_X14_Y6_N4; Fanout = 1; COMB Node = 'delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|counter_cella9~COUT'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "I2C_FPGA" "UNKNOWN" "V1" "D:/I2C_CPLD/db/I2C_FPGA.quartus_db" { Floorplan "D:/I2C_CPLD/" "" "0.246 ns" { delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|counter_cella4~COUT delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|counter_cella9~COUT } "NODE_NAME" } "" } } { "db/cntr_1ub.tdf" "" { Text "D:/I2C_CPLD/db/cntr_1ub.tdf" 105 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.975 ns) 8.045 ns delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|cout 9 COMB LC_X14_Y6_N5 12 " "Info: 9: + IC(0.000 ns) + CELL(0.975 ns) = 8.045 ns; Loc. = LC_X14_Y6_N5; Fanout = 12; COMB Node = 'delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|cout'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "I2C_FPGA" "UNKNOWN" "V1" "D:/I2C_CPLD/db/I2C_FPGA.quartus_db" { Floorplan "D:/I2C_CPLD/" "" "0.975 ns" { delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|counter_cella9~COUT delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|cout } "NODE_NAME" } "" } } { "db/cntr_1ub.tdf" "" { Text "D:/I2C_CPLD/db/cntr_1ub.tdf" 157 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 8.550 ns delay_reset_block:inst2\|inst4 10 COMB LC_X14_Y6_N6 6 " "Info: 10: + IC(0.305 ns) + CELL(0.200 ns) = 8.550 ns; Loc. = LC_X14_Y6_N6; Fanout = 6; COMB Node = 'delay_reset_block:inst2\|inst4'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "I2C_FPGA" "UNKNOWN" "V1" "D:/I2C_CPLD/db/I2C_FPGA.quartus_db" { Floorplan "D:/I2C_CPLD/" "" "0.505 ns" { delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|cout delay_reset_block:inst2|inst4 } "NODE_NAME" } "" } } { "delay_reset_block.bdf" "" { Schematic "D:/I2C_CPLD/delay_reset_block.bdf" { { 208 872 936 256 "inst4" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.311 ns) + CELL(0.918 ns) 13.779 ns i2c_test:inst1\|counter\[0\] 11 REG LC_X11_Y8_N4 5 " "Info: 11: + IC(4.311 ns) + CELL(0.918 ns) = 13.779 ns; Loc. = LC_X11_Y8_N4; Fanout = 5; REG Node = 'i2c_test:inst1\|counter\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "I2C_FPGA" "UNKNOWN" "V1" "D:/I2C_CPLD/db/I2C_FPGA.quartus_db" { Floorplan "D:/I2C_CPLD/" "" "5.229 ns" { delay_reset_block:inst2|inst4 i2c_test:inst1|counter[0] } "NODE_NAME" } "" } } { "i2c_test.v" "" { Text "D:/I2C_CPLD/i2c_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.542 ns ( 47.48 % ) " "Info: Total cell delay = 6.542 ns ( 47.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.237 ns ( 52.52 % ) " "Info: Total interconnect delay = 7.237 ns ( 52.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "I2C_FPGA" "UNKNOWN" "V1" "D:/I2C_CPLD/db/I2C_FPGA.quartus_db" { Floorplan "D:/I2C_CPLD/" "" "13.779 ns" { clk delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|safe_q[0] delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|counter_cella0~COUT delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|counter_cella1~COUT delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|counter_cella2~COUT delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|counter_cella3~COUT delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|counter_cella4~COUT delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|counter_cella9~COUT delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|cout delay_reset_block:inst2|inst4 i2c_test:inst1|counter[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "13.779 ns" { clk clk~combout delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|safe_q[0] delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|counter_cella0~COUT delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|counter_cella1~COUT delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|counter_cella2~COUT delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|counter_cella3~COUT delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|counter_cella4~COUT delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|counter_cella9~COUT delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|cout delay_reset_block:inst2|inst4 i2c_test:inst1|counter[0] } { 0.000ns 0.000ns 1.738ns 0.883ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.305ns 4.311ns } { 0.000ns 1.163ns 1.294ns 0.978ns 0.123ns 0.123ns 0.123ns 0.399ns 0.246ns 0.975ns 0.200ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "I2C_FPGA" "UNKNOWN" "V1" "D:/I2C_CPLD/db/I2C_FPGA.quartus_db" { Floorplan "D:/I2C_CPLD/" "" "3.819 ns" { clk i2c:inst4|writeData_reg[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout i2c:inst4|writeData_reg[0] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "I2C_FPGA" "UNKNOWN" "V1" "D:/I2C_CPLD/db/I2C_FPGA.quartus_db" { Floorplan "D:/I2C_CPLD/" "" "13.779 ns" { clk delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|safe_q[0] delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|counter_cella0~COUT delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|counter_cella1~COUT delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|counter_cella2~COUT delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|counter_cella3~COUT delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|counter_cella4~COUT delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|counter_cella9~COUT delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|cout delay_reset_block:inst2|inst4 i2c_test:inst1|counter[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "13.779 ns" { clk clk~combout delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|safe_q[0] delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|counter_cella0~COUT delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|counter_cella1~COUT delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|counter_cella2~COUT delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|counter_cella3~COUT delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|counter_cella4~COUT delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|counter_cella9~COUT delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|cout delay_reset_block:inst2|inst4 i2c_test:inst1|counter[0] } { 0.000ns 0.000ns 1.738ns 0.883ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.305ns 4.311ns } { 0.000ns 1.163ns 1.294ns 0.978ns 0.123ns 0.123ns 0.123ns 0.399ns 0.246ns 0.975ns 0.200ns 0.918ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "i2c_test.v" "" { Text "D:/I2C_CPLD/i2c_test.v" 17 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 699 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "I2C_FPGA" "UNKNOWN" "V1" "D:/I2C_CPLD/db/I2C_FPGA.quartus_db" { Floorplan "D:/I2C_CPLD/" "" "1.832 ns" { i2c_test:inst1|counter[0] i2c:inst4|writeData_reg[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "1.832 ns" { i2c_test:inst1|counter[0] i2c:inst4|writeData_reg[0] } { 0.000ns 1.028ns } { 0.000ns 0.804ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "I2C_FPGA" "UNKNOWN" "V1" "D:/I2C_CPLD/db/I2C_FPGA.quartus_db" { Floorplan "D:/I2C_CPLD/" "" "3.819 ns" { clk i2c:inst4|writeData_reg[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout i2c:inst4|writeData_reg[0] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "I2C_FPGA" "UNKNOWN" "V1" "D:/I2C_CPLD/db/I2C_FPGA.quartus_db" { Floorplan "D:/I2C_CPLD/" "" "13.779 ns" { clk delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|safe_q[0] delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|counter_cella0~COUT delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|counter_cella1~COUT delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|counter_cella2~COUT delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|counter_cella3~COUT delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|counter_cella4~COUT delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|counter_cella9~COUT delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|cout delay_reset_block:inst2|inst4 i2c_test:inst1|counter[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "13.779 ns" { clk clk~combout delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|safe_q[0] delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|counter_cella0~COUT delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|counter_cella1~COUT delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|counter_cella2~COUT delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|counter_cella3~COUT delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|counter_cella4~COUT delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|counter_cella9~COUT delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|cout delay_reset_block:inst2|inst4 i2c_test:inst1|counter[0] } { 0.000ns 0.000ns 1.738ns 0.883ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.305ns 4.311ns } { 0.000ns 1.163ns 1.294ns 0.978ns 0.123ns 0.123ns 0.123ns 0.399ns 0.246ns 0.975ns 0.200ns 0.918ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "write register register i2c_test:inst1\|counter\[3\] i2c_test:inst1\|counter\[3\] 304.04 MHz Internal " "Info: Clock \"write\" Internal fmax is restricted to 304.04 MHz between source register \"i2c_test:inst1\|counter\[3\]\" and destination register \"i2c_test:inst1\|counter\[3\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 3.289 ns " "Info: fmax restricted to clock pin edge rate 3.289 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.077 ns + Longest register register " "Info: + Longest register to register delay is 2.077 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns i2c_test:inst1\|counter\[3\] 1 REG LC_X11_Y8_N3 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X11_Y8_N3; Fanout = 2; REG Node = 'i2c_test:inst1\|counter\[3\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "I2C_FPGA" "UNKNOWN" "V1" "D:/I2C_CPLD/db/I2C_FPGA.quartus_db" { Floorplan "D:/I2C_CPLD/" "" "" { i2c_test:inst1|counter[3] } "NODE_NAME" } "" } } { "i2c_test.v" "" { Text "D:/I2C_CPLD/i2c_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.894 ns) + CELL(1.183 ns) 2.077 ns i2c_test:inst1\|counter\[3\] 2 REG LC_X11_Y8_N3 2 " "Info: 2: + IC(0.894 ns) + CELL(1.183 ns) = 2.077 ns; Loc. = LC_X11_Y8_N3; Fanout = 2; REG Node = 'i2c_test:inst1\|counter\[3\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "I2C_FPGA" "UNKNOWN" "V1" "D:/I2C_CPLD/db/I2C_FPGA.quartus_db" { Floorplan "D:/I2C_CPLD/" "" "2.077 ns" { i2c_test:inst1|counter[3] i2c_test:inst1|counter[3] } "NODE_NAME" } "" } } { "i2c_test.v" "" { Text "D:/I2C_CPLD/i2c_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.183 ns ( 56.96 % ) " "Info: Total cell delay = 1.183 ns ( 56.96 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.894 ns ( 43.04 % ) " "Info: Total interconnect delay = 0.894 ns ( 43.04 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "I2C_FPGA" "UNKNOWN" "V1" "D:/I2C_CPLD/db/I2C_FPGA.quartus_db" { Floorplan "D:/I2C_CPLD/" "" "2.077 ns" { i2c_test:inst1|counter[3] i2c_test:inst1|counter[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.077 ns" { i2c_test:inst1|counter[3] i2c_test:inst1|counter[3] } { 0.000ns 0.894ns } { 0.000ns 1.183ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "write destination 8.972 ns + Shortest register " "Info: + Shortest clock path from clock \"write\" to destination register is 8.972 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns write 1 CLK PIN_94 12 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_94; Fanout = 12; CLK Node = 'write'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "I2C_FPGA" "UNKNOWN" "V1" "D:/I2C_CPLD/db/I2C_FPGA.quartus_db" { Floorplan "D:/I2C_CPLD/" "" "" { write } "NODE_NAME" } "" } } { "I2C_FPGA.bdf" "" { Schematic "D:/I2C_CPLD/I2C_FPGA.bdf" { { 48 -128 40 64 "write" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.871 ns) + CELL(0.740 ns) 3.743 ns delay_reset_block:inst2\|inst4 2 COMB LC_X14_Y6_N6 6 " "Info: 2: + IC(1.871 ns) + CELL(0.740 ns) = 3.743 ns; Loc. = LC_X14_Y6_N6; Fanout = 6; COMB Node = 'delay_reset_block:inst2\|inst4'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "I2C_FPGA" "UNKNOWN" "V1" "D:/I2C_CPLD/db/I2C_FPGA.quartus_db" { Floorplan "D:/I2C_CPLD/" "" "2.611 ns" { write delay_reset_block:inst2|inst4 } "NODE_NAME" } "" } } { "delay_reset_block.bdf" "" { Schematic "D:/I2C_CPLD/delay_reset_block.bdf" { { 208 872 936 256 "inst4" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.311 ns) + CELL(0.918 ns) 8.972 ns i2c_test:inst1\|counter\[3\] 3 REG LC_X11_Y8_N3 2 " "Info: 3: + IC(4.311 ns) + CELL(0.918 ns) = 8.972 ns; Loc. = LC_X11_Y8_N3; Fanout = 2; REG Node = 'i2c_test:inst1\|counter\[3\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "I2C_FPGA" "UNKNOWN" "V1" "D:/I2C_CPLD/db/I2C_FPGA.quartus_db" { Floorplan "D:/I2C_CPLD/" "" "5.229 ns" { delay_reset_block:inst2|inst4 i2c_test:inst1|counter[3] } "NODE_NAME" } "" } } { "i2c_test.v" "" { Text "D:/I2C_CPLD/i2c_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.790 ns ( 31.10 % ) " "Info: Total cell delay = 2.790 ns ( 31.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.182 ns ( 68.90 % ) " "Info: Total interconnect delay = 6.182 ns ( 68.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "I2C_FPGA" "UNKNOWN" "V1" "D:/I2C_CPLD/db/I2C_FPGA.quartus_db" { Floorplan "D:/I2C_CPLD/" "" "8.972 ns" { write delay_reset_block:inst2|inst4 i2c_test:inst1|counter[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "8.972 ns" { write write~combout delay_reset_block:inst2|inst4 i2c_test:inst1|counter[3] } { 0.000ns 0.000ns 1.871ns 4.311ns } { 0.000ns 1.132ns 0.740ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "write source 8.972 ns - Longest register " "Info: - Longest clock path from clock \"write\" to source register is 8.972 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns write 1 CLK PIN_94 12 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_94; Fanout = 12; CLK Node = 'write'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "I2C_FPGA" "UNKNOWN" "V1" "D:/I2C_CPLD/db/I2C_FPGA.quartus_db" { Floorplan "D:/I2C_CPLD/" "" "" { write } "NODE_NAME" } "" } } { "I2C_FPGA.bdf" "" { Schematic "D:/I2C_CPLD/I2C_FPGA.bdf" { { 48 -128 40 64 "write" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.871 ns) + CELL(0.740 ns) 3.743 ns delay_reset_block:inst2\|inst4 2 COMB LC_X14_Y6_N6 6 " "Info: 2: + IC(1.871 ns) + CELL(0.740 ns) = 3.743 ns; Loc. = LC_X14_Y6_N6; Fanout = 6; COMB Node = 'delay_reset_block:inst2\|inst4'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "I2C_FPGA" "UNKNOWN" "V1" "D:/I2C_CPLD/db/I2C_FPGA.quartus_db" { Floorplan "D:/I2C_CPLD/" "" "2.611 ns" { write delay_reset_block:inst2|inst4 } "NODE_NAME" } "" } } { "delay_reset_block.bdf" "" { Schematic "D:/I2C_CPLD/delay_reset_block.bdf" { { 208 872 936 256 "inst4" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.311 ns) + CELL(0.918 ns) 8.972 ns i2c_test:inst1\|counter\[3\] 3 REG LC_X11_Y8_N3 2 " "Info: 3: + IC(4.311 ns) + CELL(0.918 ns) = 8.972 ns; Loc. = LC_X11_Y8_N3; Fanout = 2; REG Node = 'i2c_test:inst1\|counter\[3\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "I2C_FPGA" "UNKNOWN" "V1" "D:/I2C_CPLD/db/I2C_FPGA.quartus_db" { Floorplan "D:/I2C_CPLD/" "" "5.229 ns" { delay_reset_block:inst2|inst4 i2c_test:inst1|counter[3] } "NODE_NAME" } "" } } { "i2c_test.v" "" { Text "D:/I2C_CPLD/i2c_test.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.790 ns ( 31.10 % ) " "Info: Total cell delay = 2.790 ns ( 31.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.182 ns ( 68.90 % ) " "Info: Total interconnect delay = 6.182 ns ( 68.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "I2C_FPGA" "UNKNOWN" "V1" "D:/I2C_CPLD/db/I2C_FPGA.quartus_db" { Floorplan "D:/I2C_CPLD/" "" "8.972 ns" { write delay_reset_block:inst2|inst4 i2c_test:inst1|counter[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "8.972 ns" { write write~combout delay_reset_block:inst2|inst4 i2c_test:inst1|counter[3] } { 0.000ns 0.000ns 1.871ns 4.311ns } { 0.000ns 1.132ns 0.740ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "I2C_FPGA" "UNKNOWN" "V1" "D:/I2C_CPLD/db/I2C_FPGA.quartus_db" { Floorplan "D:/I2C_CPLD/" "" "8.972 ns" { write delay_reset_block:inst2|inst4 i2c_test:inst1|counter[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "8.972 ns" { write write~combout delay_reset_block:inst2|inst4 i2c_test:inst1|counter[3] } { 0.000ns 0.000ns 1.871ns 4.311ns } { 0.000ns 1.132ns 0.740ns 0.918ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "I2C_FPGA" "UNKNOWN" "V1" "D:/I2C_CPLD/db/I2C_FPGA.quartus_db" { Floorplan "D:/I2C_CPLD/" "" "8.972 ns" { write delay_reset_block:inst2|inst4 i2c_test:inst1|counter[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "8.972 ns" { write write~combout delay_reset_block:inst2|inst4 i2c_test:inst1|counter[3] } { 0.000ns 0.000ns 1.871ns 4.311ns } { 0.000ns 1.132ns 0.740ns 0.918ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "i2c_test.v" "" { Text "D:/I2C_CPLD/i2c_test.v" 17 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "i2c_test.v" "" { Text "D:/I2C_CPLD/i2c_test.v" 17 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "I2C_FPGA" "UNKNOWN" "V1" "D:/I2C_CPLD/db/I2C_FPGA.quartus_db" { Floorplan "D:/I2C_CPLD/" "" "2.077 ns" { i2c_test:inst1|counter[3] i2c_test:inst1|counter[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.077 ns" { i2c_test:inst1|counter[3] i2c_test:inst1|counter[3] } { 0.000ns 0.894ns } { 0.000ns 1.183ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "I2C_FPGA" "UNKNOWN" "V1" "D:/I2C_CPLD/db/I2C_FPGA.quartus_db" { Floorplan "D:/I2C_CPLD/" "" "8.972 ns" { write delay_reset_block:inst2|inst4 i2c_test:inst1|counter[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "8.972 ns" { write write~combout delay_reset_block:inst2|inst4 i2c_test:inst1|counter[3] } { 0.000ns 0.000ns 1.871ns 4.311ns } { 0.000ns 1.132ns 0.740ns 0.918ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "I2C_FPGA" "UNKNOWN" "V1" "D:/I2C_CPLD/db/I2C_FPGA.quartus_db" { Floorplan "D:/I2C_CPLD/" "" "8.972 ns" { write delay_reset_block:inst2|inst4 i2c_test:inst1|counter[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "8.972 ns" { write write~combout delay_reset_block:inst2|inst4 i2c_test:inst1|counter[3] } { 0.000ns 0.000ns 1.871ns 4.311ns } { 0.000ns 1.132ns 0.740ns 0.918ns } } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "I2C_FPGA" "UNKNOWN" "V1" "D:/I2C_CPLD/db/I2C_FPGA.quartus_db" { Floorplan "D:/I2C_CPLD/" "" "" { i2c_test:inst1|counter[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { i2c_test:inst1|counter[3] } {  } {  } } } { "i2c_test.v" ""