i2c_fpga.tan.qmsg

Verilog 经典实例

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "I2C_FPGA.bdf" "" { Schematic "D:/I2C_CPLD/I2C_FPGA.bdf" { { -96 -104 64 -80 "clk" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "write " "Info: Assuming node \"write\" is an undefined clock" {  } { { "I2C_FPGA.bdf" "" { Schematic "D:/I2C_CPLD/I2C_FPGA.bdf" { { 48 -128 40 64 "write" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "write" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "33 " "Warning: Found 33 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|safe_q\[0\] " "Info: Detected ripple clock \"delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|safe_q\[0\]\" as buffer" {  } { { "db/cntr_1ub.tdf" "" { Text "D:/I2C_CPLD/db/cntr_1ub.tdf" 125 8 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|safe_q\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|counter_cella1~COUTCOUT1_4 " "Info: Detected gated clock \"delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|counter_cella1~COUTCOUT1_4\" as buffer" {  } { { "db/cntr_1ub.tdf" "" { Text "D:/I2C_CPLD/db/cntr_1ub.tdf" 41 2 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|counter_cella1~COUTCOUT1_4" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|safe_q\[1\] " "Info: Detected ripple clock \"delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|safe_q\[1\]\" as buffer" {  } { { "db/cntr_1ub.tdf" "" { Text "D:/I2C_CPLD/db/cntr_1ub.tdf" 125 8 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|safe_q\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|counter_cella2~COUTCOUT1_4 " "Info: Detected gated clock \"delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|counter_cella2~COUTCOUT1_4\" as buffer" {  } { { "db/cntr_1ub.tdf" "" { Text "D:/I2C_CPLD/db/cntr_1ub.tdf" 49 2 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|counter_cella2~COUTCOUT1_4" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|counter_cella1~COUT " "Info: Detected gated clock \"delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|counter_cella1~COUT\" as buffer" {  } { { "db/cntr_1ub.tdf" "" { Text "D:/I2C_CPLD/db/cntr_1ub.tdf" 41 2 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|counter_cella1~COUT" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|safe_q\[2\] " "Info: Detected ripple clock \"delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|safe_q\[2\]\" as buffer" {  } { { "db/cntr_1ub.tdf" "" { Text "D:/I2C_CPLD/db/cntr_1ub.tdf" 125 8 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|safe_q\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|counter_cella2~COUT " "Info: Detected gated clock \"delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|counter_cella2~COUT\" as buffer" {  } { { "db/cntr_1ub.tdf" "" { Text "D:/I2C_CPLD/db/cntr_1ub.tdf" 49 2 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|counter_cella2~COUT" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|safe_q\[3\] " "Info: Detected ripple clock \"delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|safe_q\[3\]\" as buffer" {  } { { "db/cntr_1ub.tdf" "" { Text "D:/I2C_CPLD/db/cntr_1ub.tdf" 125 8 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|safe_q\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|safe_q\[5\] " "Info: Detected ripple clock \"delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|safe_q\[5\]\" as buffer" {  } { { "db/cntr_1ub.tdf" "" { Text "D:/I2C_CPLD/db/cntr_1ub.tdf" 125 8 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|safe_q\[5\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|counter_cella6~COUTCOUT1_4 " "Info: Detected gated clock \"delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|counter_cella6~COUTCOUT1_4\" as buffer" {  } { { "db/cntr_1ub.tdf" "" { Text "D:/I2C_CPLD/db/cntr_1ub.tdf" 81 2 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|counter_cella6~COUTCOUT1_4" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|safe_q\[6\] " "Info: Detected ripple clock \"delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|safe_q\[6\]\" as buffer" {  } { { "db/cntr_1ub.tdf" "" { Text "D:/I2C_CPLD/db/cntr_1ub.tdf" 125 8 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|safe_q\[6\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|counter_cella7~COUTCOUT1_4 " "Info: Detected gated clock \"delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|counter_cella7~COUTCOUT1_4\" as buffer" {  } { { "db/cntr_1ub.tdf" "" { Text "D:/I2C_CPLD/db/cntr_1ub.tdf" 89 2 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|counter_cella7~COUTCOUT1_4" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|counter_cella6~COUT " "Info: Detected gated clock \"delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|counter_cella6~COUT\" as buffer" {  } { { "db/cntr_1ub.tdf" "" { Text "D:/I2C_CPLD/db/cntr_1ub.tdf" 81 2 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|counter_cella6~COUT" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|safe_q\[7\] " "Info: Detected ripple clock \"delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|safe_q\[7\]\" as buffer" {  } { { "db/cntr_1ub.tdf" "" { Text "D:/I2C_CPLD/db/cntr_1ub.tdf" 125 8 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|safe_q\[7\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|counter_cella7~COUT " "Info: Detected gated clock \"delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|counter_cella7~COUT\" as buffer" {  } { { "db/cntr_1ub.tdf" "" { Text "D:/I2C_CPLD/db/cntr_1ub.tdf" 89 2 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|counter_cella7~COUT" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|safe_q\[8\] " "Info: Detected ripple clock \"delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|safe_q\[8\]\" as buffer" {  } { { "db/cntr_1ub.tdf" "" { Text "D:/I2C_CPLD/db/cntr_1ub.tdf" 125 8 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|safe_q\[8\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|counter_cella3~COUTCOUT1_4 " "Info: Detected gated clock \"delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|counter_cella3~COUTCOUT1_4\" as buffer" {  } { { "db/cntr_1ub.tdf" "" { Text "D:/I2C_CPLD/db/cntr_1ub.tdf" 57 2 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|counter_cella3~COUTCOUT1_4" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|counter_cella3~COUT " "Info: Detected gated clock \"delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|counter_cella3~COUT\" as buffer" {  } { { "db/cntr_1ub.tdf" "" { Text "D:/I2C_CPLD/db/cntr_1ub.tdf" 57 2 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|counter_cella3~COUT" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|safe_q\[4\] " "Info: Detected ripple clock \"delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|safe_q\[4\]\" as buffer" {  } { { "db/cntr_1ub.tdf" "" { Text "D:/I2C_CPLD/db/cntr_1ub.tdf" 125 8 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|safe_q\[4\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|counter_cella8~COUTCOUT1_4 " "Info: Detected gated clock \"delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|counter_cella8~COUTCOUT1_4\" as buffer" {  } { { "db/cntr_1ub.tdf" "" { Text "D:/I2C_CPLD/db/cntr_1ub.tdf" 97 2 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|counter_cella8~COUTCOUT1_4" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|counter_cella8~COUT " "Info: Detected gated clock \"delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|counter_cella8~COUT\" as buffer" {  } { { "db/cntr_1ub.tdf" "" { Text "D:/I2C_CPLD/db/cntr_1ub.tdf" 97 2 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|counter_cella8~COUT" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|counter_cella4~COUT " "Info: Detected gated clock \"delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|counter_cella4~COUT\" as buffer" {  } { { "db/cntr_1ub.tdf" "" { Text "D:/I2C_CPLD/db/cntr_1ub.tdf" 65 2 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|counter_cella4~COUT" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|safe_q\[9\] " "Info: Detected ripple clock \"delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|safe_q\[9\]\" as buffer" {  } { { "db/cntr_1ub.tdf" "" { Text "D:/I2C_CPLD/db/cntr_1ub.tdf" 125 8 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|safe_q\[9\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|counter_cella9~COUT " "Info: Detected gated clock \"delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|counter_cella9~COUT\" as buffer" {  } { { "db/cntr_1ub.tdf" "" { Text "D:/I2C_CPLD/db/cntr_1ub.tdf" 105 2 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "delay_reset_block:inst2\|reset_counter:inst\|lpm_counter:lpm_counter_component\|cntr_1ub:auto_generated\|counter_cella9~COUT" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "delay_reset_block:inst2\|inst4 " "Info: Detected gated clock \"delay_reset_block:inst2\|inst4\" as buffer" {  } { { "delay_reset_block.bdf" "" { Schematic "D:/I2C_CPLD/delay_reset_block.bdf" { { 208 872 936 256 "inst4" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "delay_reset_block:inst2\|inst4" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "i2c:inst4\|reduce_or~243 " "Info: Detected gated clock \"i2c:inst4\|reduce_or~243\" as buffer" {  } { { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "i2c:inst4\|reduce_or~243" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "i2c:inst4\|reduce_or~242 " "Info: Detected gated clock \"i2c:inst4\|reduce_or~242\" as buffer" {  } { { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "i2c:inst4\|reduce_or~242" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "i2c:inst4\|readData_reg\[7\] " "Info: Detected ripple clock \"i2c:inst4\|readData_reg\[7\]\" as buffer" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 699 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "i2c:inst4\|readData_reg\[7\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "i2c:inst4\|readData_reg\[6\] " "Info: Detected ripple clock \"i2c:inst4\|readData_reg\[6\]\" as buffer" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 699 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "i2c:inst4\|readData_reg\[6\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "i2c:inst4\|readData_reg\[5\] " "Info: Detected ripple clock \"i2c:inst4\|readData_reg\[5\]\" as buffer" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 699 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "i2c:inst4\|readData_reg\[5\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "i2c:inst4\|readData_reg\[4\] " "Info: Detected ripple clock \"i2c:inst4\|readData_reg\[4\]\" as buffer" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 699 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "i2c:inst4\|readData_reg\[4\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "i2c:inst4\|en\[0\] " "Info: Detected ripple clock \"i2c:inst4\|en\[0\]\" as buffer" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 716 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "i2c:inst4\|en\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "i2c:inst4\|en\[1\] " "Info: Detected ripple clock \"i2c:inst4\|en\[1\]\" as buffer" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 716 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "i2c:inst4\|en\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}