i2c_fpga.tan.qmsg

Verilog 经典实例

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Warning" "WTAN_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTAN_COMB_LATCH_NODE" "i2c:inst4\|seg_data\[6\] " "Warning: Node \"i2c:inst4\|seg_data\[6\]\" is a latch" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 732 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "i2c:inst4\|seg_data\[5\] " "Warning: Node \"i2c:inst4\|seg_data\[5\]\" is a latch" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 732 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "i2c:inst4\|seg_data\[4\] " "Warning: Node \"i2c:inst4\|seg_data\[4\]\" is a latch" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 732 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "i2c:inst4\|seg_data\[3\] " "Warning: Node \"i2c:inst4\|seg_data\[3\]\" is a latch" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 732 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "i2c:inst4\|seg_data\[2\] " "Warning: Node \"i2c:inst4\|seg_data\[2\]\" is a latch" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 732 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "i2c:inst4\|seg_data\[1\] " "Warning: Node \"i2c:inst4\|seg_data\[1\]\" is a latch" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 732 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "i2c:inst4\|seg_data\[0\] " "Warning: Node \"i2c:inst4\|seg_data\[0\]\" is a latch" {  } { { "i2c.v" "" { Text "D:/I2C_CPLD/i2c.v" 732 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0}