da_tlc5620.sim.rpt

Verilog 经典实例

The following table displays output ports that do not toggle to 0 during simulation.
+----------------------------------------------------------------------------+
; Missing 0-Value Coverage                                                   ;
+---------------------------+-----------------------------+------------------+
; Node Name                 ; Output Port Name            ; Output Port Type ;
+---------------------------+-----------------------------+------------------+
; |tlc5620|counter[4]       ; |tlc5620|counter[4]         ; regout           ;
; |tlc5620|counter[5]       ; |tlc5620|counter[5]         ; regout           ;
; |tlc5620|DCLK_DIV[6]      ; |tlc5620|DCLK_DIV[6]        ; regout           ;
; |tlc5620|DCLK_DIV[7]      ; |tlc5620|DCLK_DIV[7]        ; regout           ;
; |tlc5620|DCLK_DIV[8]      ; |tlc5620|DCLK_DIV[8]        ; regout           ;
; |tlc5620|DCLK_DIV[9]      ; |tlc5620|DCLK_DIV[9]        ; regout           ;
; |tlc5620|DCLK_DIV[10]     ; |tlc5620|DCLK_DIV[10]       ; regout           ;
; |tlc5620|DCLK_DIV[11]     ; |tlc5620|DCLK_DIV[11]       ; regout           ;
; |tlc5620|DCLK_DIV[12]     ; |tlc5620|DCLK_DIV[12]       ; regout           ;
; |tlc5620|DCLK_DIV[13]     ; |tlc5620|DCLK_DIV[13]       ; regout           ;
; |tlc5620|DCLK_DIV[14]     ; |tlc5620|DCLK_DIV[14]       ; regout           ;
; |tlc5620|DCLK_DIV[15]     ; |tlc5620|DCLK_DIV[15]       ; regout           ;
; |tlc5620|DCLK_DIV[16]     ; |tlc5620|DCLK_DIV[16]       ; regout           ;
; |tlc5620|DCLK_DIV[17]     ; |tlc5620|DCLK_DIV[17]       ; regout           ;
; |tlc5620|DCLK_DIV[18]     ; |tlc5620|DCLK_DIV[18]       ; regout           ;
; |tlc5620|DCLK_DIV[19]     ; |tlc5620|DCLK_DIV[19]       ; regout           ;
; |tlc5620|DCLK_DIV[20]     ; |tlc5620|DCLK_DIV[20]       ; regout           ;
; |tlc5620|DCLK_DIV[21]     ; |tlc5620|DCLK_DIV[21]       ; regout           ;
; |tlc5620|DCLK_DIV[22]     ; |tlc5620|DCLK_DIV[22]       ; regout           ;
; |tlc5620|DCLK_DIV[23]     ; |tlc5620|DCLK_DIV[23]       ; regout           ;
; |tlc5620|DCLK_DIV[24]     ; |tlc5620|DCLK_DIV[24]       ; regout           ;
; |tlc5620|DCLK_DIV[25]     ; |tlc5620|DCLK_DIV[25]       ; regout           ;
; |tlc5620|DCLK_DIV[26]     ; |tlc5620|DCLK_DIV[26]       ; regout           ;
; |tlc5620|DCLK_DIV[27]     ; |tlc5620|DCLK_DIV[27]       ; regout           ;
; |tlc5620|DCLK_DIV[28]     ; |tlc5620|DCLK_DIV[28]       ; regout           ;
; |tlc5620|DCLK_DIV[29]     ; |tlc5620|DCLK_DIV[29]       ; regout           ;
; |tlc5620|DCLK_DIV[30]     ; |tlc5620|DCLK_DIV[30]       ; regout           ;
; |tlc5620|DCLK_DIV[31]     ; |tlc5620|DCLK_DIV[31]       ; regout           ;
; |tlc5620|counter[4]~123   ; |tlc5620|counter[4]~124     ; cout             ;
; |tlc5620|counter[5]~125   ; |tlc5620|counter[5]~125     ; combout          ;
; |tlc5620|DCLK_DIV[6]~379  ; |tlc5620|DCLK_DIV[6]~380    ; cout             ;
; |tlc5620|DCLK_DIV[7]~381  ; |tlc5620|DCLK_DIV[7]~381    ; combout          ;
; |tlc5620|DCLK_DIV[7]~381  ; |tlc5620|DCLK_DIV[7]~382    ; cout             ;
; |tlc5620|DCLK_DIV[8]~383  ; |tlc5620|DCLK_DIV[8]~383    ; combout          ;
; |tlc5620|DCLK_DIV[8]~383  ; |tlc5620|DCLK_DIV[8]~384    ; cout             ;
; |tlc5620|DCLK_DIV[9]~385  ; |tlc5620|DCLK_DIV[9]~385    ; combout          ;
; |tlc5620|DCLK_DIV[9]~385  ; |tlc5620|DCLK_DIV[9]~386    ; cout             ;
; |tlc5620|DCLK_DIV[10]~387 ; |tlc5620|DCLK_DIV[10]~387   ; combout          ;
; |tlc5620|DCLK_DIV[10]~387 ; |tlc5620|DCLK_DIV[10]~388   ; cout             ;
; |tlc5620|DCLK_DIV[11]~389 ; |tlc5620|DCLK_DIV[11]~389   ; combout          ;
; |tlc5620|DCLK_DIV[11]~389 ; |tlc5620|DCLK_DIV[11]~390   ; cout             ;
; |tlc5620|DCLK_DIV[12]~391 ; |tlc5620|DCLK_DIV[12]~391   ; combout          ;
; |tlc5620|DCLK_DIV[12]~391 ; |tlc5620|DCLK_DIV[12]~392   ; cout             ;
; |tlc5620|DCLK_DIV[13]~393 ; |tlc5620|DCLK_DIV[13]~393   ; combout          ;
; |tlc5620|DCLK_DIV[13]~393 ; |tlc5620|DCLK_DIV[13]~394   ; cout             ;
; |tlc5620|DCLK_DIV[14]~395 ; |tlc5620|DCLK_DIV[14]~395   ; combout          ;
; |tlc5620|DCLK_DIV[14]~395 ; |tlc5620|DCLK_DIV[14]~396   ; cout             ;
; |tlc5620|DCLK_DIV[15]~397 ; |tlc5620|DCLK_DIV[15]~397   ; combout          ;
; |tlc5620|DCLK_DIV[15]~397 ; |tlc5620|DCLK_DIV[15]~398   ; cout             ;
; |tlc5620|DCLK_DIV[16]~399 ; |tlc5620|DCLK_DIV[16]~399   ; combout          ;
; |tlc5620|DCLK_DIV[16]~399 ; |tlc5620|DCLK_DIV[16]~400   ; cout             ;
; |tlc5620|DCLK_DIV[17]~401 ; |tlc5620|DCLK_DIV[17]~401   ; combout          ;
; |tlc5620|DCLK_DIV[17]~401 ; |tlc5620|DCLK_DIV[17]~402   ; cout             ;
; |tlc5620|DCLK_DIV[18]~403 ; |tlc5620|DCLK_DIV[18]~403   ; combout          ;
; |tlc5620|DCLK_DIV[18]~403 ; |tlc5620|DCLK_DIV[18]~404   ; cout             ;
; |tlc5620|DCLK_DIV[19]~405 ; |tlc5620|DCLK_DIV[19]~405   ; combout          ;
; |tlc5620|DCLK_DIV[19]~405 ; |tlc5620|DCLK_DIV[19]~406   ; cout             ;
; |tlc5620|DCLK_DIV[20]~407 ; |tlc5620|DCLK_DIV[20]~407   ; combout          ;
; |tlc5620|DCLK_DIV[20]~407 ; |tlc5620|DCLK_DIV[20]~408   ; cout             ;
; |tlc5620|DCLK_DIV[21]~409 ; |tlc5620|DCLK_DIV[21]~409   ; combout          ;
; |tlc5620|DCLK_DIV[21]~409 ; |tlc5620|DCLK_DIV[21]~410   ; cout             ;
; |tlc5620|DCLK_DIV[22]~411 ; |tlc5620|DCLK_DIV[22]~411   ; combout          ;
; |tlc5620|DCLK_DIV[22]~411 ; |tlc5620|DCLK_DIV[22]~412   ; cout             ;
; |tlc5620|DCLK_DIV[23]~413 ; |tlc5620|DCLK_DIV[23]~413   ; combout          ;
; |tlc5620|DCLK_DIV[23]~413 ; |tlc5620|DCLK_DIV[23]~414   ; cout             ;
; |tlc5620|DCLK_DIV[24]~415 ; |tlc5620|DCLK_DIV[24]~415   ; combout          ;
; |tlc5620|DCLK_DIV[24]~415 ; |tlc5620|DCLK_DIV[24]~416   ; cout             ;
; |tlc5620|DCLK_DIV[25]~417 ; |tlc5620|DCLK_DIV[25]~417   ; combout          ;
; |tlc5620|DCLK_DIV[25]~417 ; |tlc5620|DCLK_DIV[25]~418   ; cout             ;
; |tlc5620|DCLK_DIV[26]~419 ; |tlc5620|DCLK_DIV[26]~419   ; combout          ;
; |tlc5620|DCLK_DIV[26]~419 ; |tlc5620|DCLK_DIV[26]~420   ; cout             ;
; |tlc5620|DCLK_DIV[27]~421 ; |tlc5620|DCLK_DIV[27]~421   ; combout          ;
; |tlc5620|DCLK_DIV[27]~421 ; |tlc5620|DCLK_DIV[27]~422   ; cout             ;
; |tlc5620|DCLK_DIV[28]~423 ; |tlc5620|DCLK_DIV[28]~423   ; combout          ;
; |tlc5620|DCLK_DIV[28]~423 ; |tlc5620|DCLK_DIV[28]~424   ; cout             ;
; |tlc5620|DCLK_DIV[29]~425 ; |tlc5620|DCLK_DIV[29]~425   ; combout          ;
; |tlc5620|DCLK_DIV[29]~425 ; |tlc5620|DCLK_DIV[29]~426   ; cout             ;
; |tlc5620|DCLK_DIV[30]~427 ; |tlc5620|DCLK_DIV[30]~427   ; combout          ;
; |tlc5620|DCLK_DIV[30]~427 ; |tlc5620|DCLK_DIV[30]~428   ; cout             ;
; |tlc5620|DCLK_DIV[31]~429 ; |tlc5620|DCLK_DIV[31]~429   ; combout          ;
; |tlc5620|dac_clk~125      ; |tlc5620|dac_clk~125        ; combout          ;
; |tlc5620|dac_data_r~271   ; |tlc5620|dac_data_r~271     ; combout          ;
; |tlc5620|LessThan0~500    ; |tlc5620|LessThan0~500      ; combout          ;
; |tlc5620|LessThan0~501    ; |tlc5620|LessThan0~501      ; combout          ;
; |tlc5620|LessThan0~504    ; |tlc5620|LessThan0~504      ; combout          ;
; |tlc5620|LessThan0~505    ; |tlc5620|LessThan0~505      ; combout          ;
; |tlc5620|LessThan0~506    ; |tlc5620|LessThan0~506      ; combout          ;
; |tlc5620|LessThan0~507    ; |tlc5620|LessThan0~507      ; combout          ;
; |tlc5620|LessThan0~508    ; |tlc5620|LessThan0~508      ; combout          ;
; |tlc5620|wr_data[9]       ; |tlc5620|wr_data[9]~corein  ; combout          ;
; |tlc5620|wr_data[10]      ; |tlc5620|wr_data[10]~corein ; combout          ;
; |tlc5620|wr_data[8]       ; |tlc5620|wr_data[8]~corein  ; combout          ;
; |tlc5620|wr_data[1]       ; |tlc5620|wr_data[1]~corein  ; combout          ;
; |tlc5620|wr_data[2]       ; |tlc5620|wr_data[2]~corein  ; combout          ;
; |tlc5620|wr_data[3]       ; |tlc5620|wr_data[3]~corein  ; combout          ;
; |tlc5620|wr_data[0]       ; |tlc5620|wr_data[0]~corein  ; combout          ;
; |tlc5620|wr_data[6]       ; |tlc5620|wr_data[6]~corein  ; combout          ;
; |tlc5620|wr_data[5]       ; |tlc5620|wr_data[5]~corein  ; combout          ;
; |tlc5620|wr_data[7]       ; |tlc5620|wr_data[7]~corein  ; combout          ;
; |tlc5620|wr_data[4]       ; |tlc5620|wr_data[4]~corein  ; combout          ;
; |tlc5620|write_n          ; |tlc5620|write_n~corein     ; combout          ;
; |tlc5620|rst              ; |tlc5620|rst~corein         ; combout          ;
; |tlc5620|rst~clkctrl      ; |tlc5620|rst~clkctrl        ; outclk           ;
+---------------------------+-----------------------------+------------------+


+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage      ;
+--------+------------+


+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
    Info: Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version
    Info: Processing started: Mon Jan 14 15:47:01 2008
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off DA_TLC5620 -c DA_TLC5620
Info: Using vector source file "G:/Q71/verilog/DA_TLC5620/DA_TLC5620.vwf"
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
    Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is      36.02 %
Info: Number of transitions in simulation is 1344017
Info: Quartus II Simulator was successful. 0 errors, 0 warnings
    Info: Allocated 102 megabytes of memory during processing
    Info: Processing ended: Mon Jan 14 15:47:16 2008
    Info: Elapsed time: 00:00:15