lcd_1602.tan.qmsg

Verilog 经典实例

{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "lcd:inst\|clk_int lcd:inst\|clk_int clk 3.806 ns " "Info: Found hold time violation between source  pin or register \"lcd:inst\|clk_int\" and destination pin or register \"lcd:inst\|clk_int\" for clock \"clk\" (Hold time is 3.806 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "5.446 ns + Largest " "Info: + Largest clock skew is 5.446 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 19.063 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 19.063 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 21 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 21; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_1602" "UNKNOWN" "V1" "D:/lcd_1602/db/lcd_1602.quartus_db" { Floorplan "D:/lcd_1602/" "" "" { clk } "NODE_NAME" } "" } } { "lcd_1602.bdf" "" { Schematic "D:/lcd_1602/lcd_1602.bdf" { { 48 64 232 64 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns lcd:inst\|clkcnt\[14\] 2 REG LC_X15_Y6_N9 3 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X15_Y6_N9; Fanout = 3; REG Node = 'lcd:inst\|clkcnt\[14\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_1602" "UNKNOWN" "V1" "D:/lcd_1602/db/lcd_1602.quartus_db" { Floorplan "D:/lcd_1602/" "" "3.032 ns" { clk lcd:inst|clkcnt[14] } "NODE_NAME" } "" } } { "lcd.v" "" { Text "D:/lcd_1602/lcd.v" 64 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.245 ns) + CELL(0.914 ns) 6.354 ns lcd:inst\|Equal~337 3 COMB LC_X16_Y6_N9 1 " "Info: 3: + IC(1.245 ns) + CELL(0.914 ns) = 6.354 ns; Loc. = LC_X16_Y6_N9; Fanout = 1; COMB Node = 'lcd:inst\|Equal~337'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_1602" "UNKNOWN" "V1" "D:/lcd_1602/db/lcd_1602.quartus_db" { Floorplan "D:/lcd_1602/" "" "2.159 ns" { lcd:inst|clkcnt[14] lcd:inst|Equal~337 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.817 ns) + CELL(0.914 ns) 9.085 ns lcd:inst\|Equal~338 4 COMB LC_X14_Y6_N3 2 " "Info: 4: + IC(1.817 ns) + CELL(0.914 ns) = 9.085 ns; Loc. = LC_X14_Y6_N3; Fanout = 2; COMB Node = 'lcd:inst\|Equal~338'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_1602" "UNKNOWN" "V1" "D:/lcd_1602/db/lcd_1602.quartus_db" { Floorplan "D:/lcd_1602/" "" "2.731 ns" { lcd:inst|Equal~337 lcd:inst|Equal~338 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.688 ns) + CELL(0.511 ns) 11.284 ns lcd:inst\|Equal~340 5 COMB LC_X16_Y6_N8 1 " "Info: 5: + IC(1.688 ns) + CELL(0.511 ns) = 11.284 ns; Loc. = LC_X16_Y6_N8; Fanout = 1; COMB Node = 'lcd:inst\|Equal~340'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_1602" "UNKNOWN" "V1" "D:/lcd_1602/db/lcd_1602.quartus_db" { Floorplan "D:/lcd_1602/" "" "2.199 ns" { lcd:inst|Equal~338 lcd:inst|Equal~340 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.689 ns) + CELL(1.294 ns) 13.267 ns lcd:inst\|clkdiv 6 REG LC_X16_Y6_N6 3 " "Info: 6: + IC(0.689 ns) + CELL(1.294 ns) = 13.267 ns; Loc. = LC_X16_Y6_N6; Fanout = 3; REG Node = 'lcd:inst\|clkdiv'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_1602" "UNKNOWN" "V1" "D:/lcd_1602/db/lcd_1602.quartus_db" { Floorplan "D:/lcd_1602/" "" "1.983 ns" { lcd:inst|Equal~340 lcd:inst|clkdiv } "NODE_NAME" } "" } } { "lcd.v" "" { Text "D:/lcd_1602/lcd.v" 77 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.878 ns) + CELL(0.918 ns) 19.063 ns lcd:inst\|clk_int 7 REG LC_X12_Y3_N2 37 " "Info: 7: + IC(4.878 ns) + CELL(0.918 ns) = 19.063 ns; Loc. = LC_X12_Y3_N2; Fanout = 37; REG Node = 'lcd:inst\|clk_int'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_1602" "UNKNOWN" "V1" "D:/lcd_1602/db/lcd_1602.quartus_db" { Floorplan "D:/lcd_1602/" "" "5.796 ns" { lcd:inst|clkdiv lcd:inst|clk_int } "NODE_NAME" } "" } } { "lcd.v" "" { Text "D:/lcd_1602/lcd.v" 84 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.008 ns ( 36.76 % ) " "Info: Total cell delay = 7.008 ns ( 36.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "12.055 ns ( 63.24 % ) " "Info: Total interconnect delay = 12.055 ns ( 63.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_1602" "UNKNOWN" "V1" "D:/lcd_1602/db/lcd_1602.quartus_db" { Floorplan "D:/lcd_1602/" "" "19.063 ns" { clk lcd:inst|clkcnt[14] lcd:inst|Equal~337 lcd:inst|Equal~338 lcd:inst|Equal~340 lcd:inst|clkdiv lcd:inst|clk_int } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "19.063 ns" { clk clk~combout lcd:inst|clkcnt[14] lcd:inst|Equal~337 lcd:inst|Equal~338 lcd:inst|Equal~340 lcd:inst|clkdiv lcd:inst|clk_int } { 0.000ns 0.000ns 1.738ns 1.245ns 1.817ns 1.688ns 0.689ns 4.878ns } { 0.000ns 1.163ns 1.294ns 0.914ns 0.914ns 0.511ns 1.294ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 13.617 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 13.617 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 21 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 21; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_1602" "UNKNOWN" "V1" "D:/lcd_1602/db/lcd_1602.quartus_db" { Floorplan "D:/lcd_1602/" "" "" { clk } "NODE_NAME" } "" } } { "lcd_1602.bdf" "" { Schematic "D:/lcd_1602/lcd_1602.bdf" { { 48 64 232 64 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns lcd:inst\|clkcnt\[18\] 2 REG LC_X16_Y6_N3 4 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X16_Y6_N3; Fanout = 4; REG Node = 'lcd:inst\|clkcnt\[18\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_1602" "UNKNOWN" "V1" "D:/lcd_1602/db/lcd_1602.quartus_db" { Floorplan "D:/lcd_1602/" "" "3.032 ns" { clk lcd:inst|clkcnt[18] } "NODE_NAME" } "" } } { "lcd.v" "" { Text "D:/lcd_1602/lcd.v" 64 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.938 ns) + CELL(0.200 ns) 5.333 ns lcd:inst\|Equal~339 3 COMB LC_X16_Y6_N7 2 " "Info: 3: + IC(0.938 ns) + CELL(0.200 ns) = 5.333 ns; Loc. = LC_X16_Y6_N7; Fanout = 2; COMB Node = 'lcd:inst\|Equal~339'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_1602" "UNKNOWN" "V1" "D:/lcd_1602/db/lcd_1602.quartus_db" { Floorplan "D:/lcd_1602/" "" "1.138 ns" { lcd:inst|clkcnt[18] lcd:inst|Equal~339 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 5.838 ns lcd:inst\|Equal~340 4 COMB LC_X16_Y6_N8 1 " "Info: 4: + IC(0.305 ns) + CELL(0.200 ns) = 5.838 ns; Loc. = LC_X16_Y6_N8; Fanout = 1; COMB Node = 'lcd:inst\|Equal~340'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_1602" "UNKNOWN" "V1" "D:/lcd_1602/db/lcd_1602.quartus_db" { Floorplan "D:/lcd_1602/" "" "0.505 ns" { lcd:inst|Equal~339 lcd:inst|Equal~340 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.689 ns) + CELL(1.294 ns) 7.821 ns lcd:inst\|clkdiv 5 REG LC_X16_Y6_N6 3 " "Info: 5: + IC(0.689 ns) + CELL(1.294 ns) = 7.821 ns; Loc. = LC_X16_Y6_N6; Fanout = 3; REG Node = 'lcd:inst\|clkdiv'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_1602" "UNKNOWN" "V1" "D:/lcd_1602/db/lcd_1602.quartus_db" { Floorplan "D:/lcd_1602/" "" "1.983 ns" { lcd:inst|Equal~340 lcd:inst|clkdiv } "NODE_NAME" } "" } } { "lcd.v" "" { Text "D:/lcd_1602/lcd.v" 77 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.878 ns) + CELL(0.918 ns) 13.617 ns lcd:inst\|clk_int 6 REG LC_X12_Y3_N2 37 " "Info: 6: + IC(4.878 ns) + CELL(0.918 ns) = 13.617 ns; Loc. = LC_X12_Y3_N2; Fanout = 37; REG Node = 'lcd:inst\|clk_int'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_1602" "UNKNOWN" "V1" "D:/lcd_1602/db/lcd_1602.quartus_db" { Floorplan "D:/lcd_1602/" "" "5.796 ns" { lcd:inst|clkdiv lcd:inst|clk_int } "NODE_NAME" } "" } } { "lcd.v" "" { Text "D:/lcd_1602/lcd.v" 84 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.069 ns ( 37.23 % ) " "Info: Total cell delay = 5.069 ns ( 37.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.548 ns ( 62.77 % ) " "Info: Total interconnect delay = 8.548 ns ( 62.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_1602" "UNKNOWN" "V1" "D:/lcd_1602/db/lcd_1602.quartus_db" { Floorplan "D:/lcd_1602/" "" "13.617 ns" { clk lcd:inst|clkcnt[18] lcd:inst|Equal~339 lcd:inst|Equal~340 lcd:inst|clkdiv lcd:inst|clk_int } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "13.617 ns" { clk clk~combout lcd:inst|clkcnt[18] lcd:inst|Equal~339 lcd:inst|Equal~340 lcd:inst|clkdiv lcd:inst|clk_int } { 0.000ns 0.000ns 1.738ns 0.938ns 0.305ns 0.689ns 4.878ns } { 0.000ns 1.163ns 1.294ns 0.200ns 0.200ns 1.294ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_1602" "UNKNOWN" "V1" "D:/lcd_1602/db/lcd_1602.quartus_db" { Floorplan "D:/lcd_1602/" "" "19.063 ns" { clk lcd:inst|clkcnt[14] lcd:inst|Equal~337 lcd:inst|Equal~338 lcd:inst|Equal~340 lcd:inst|clkdiv lcd:inst|clk_int } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "19.063 ns" { clk clk~combout lcd:inst|clkcnt[14] lcd:inst|Equal~337 lcd:inst|Equal~338 lcd:inst|Equal~340 lcd:inst|clkdiv lcd:inst|clk_int } { 0.000ns 0.000ns 1.738ns 1.245ns 1.817ns 1.688ns 0.689ns 4.878ns } { 0.000ns 1.163ns 1.294ns 0.914ns 0.914ns 0.511ns 1.294ns 0.918ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_1602" "UNKNOWN" "V1" "D:/lcd_1602/db/lcd_1602.quartus_db" { Floorplan "D:/lcd_1602/" "" "13.617 ns" { clk lcd:inst|clkcnt[18] lcd:inst|Equal~339 lcd:inst|Equal~340 lcd:inst|clkdiv lcd:inst|clk_int } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "13.617 ns" { clk clk~combout lcd:inst|clkcnt[18] lcd:inst|Equal~339 lcd:inst|Equal~340 lcd:inst|clkdiv lcd:inst|clk_int } { 0.000ns 0.000ns 1.738ns 0.938ns 0.305ns 0.689ns 4.878ns } { 0.000ns 1.163ns 1.294ns 0.200ns 0.200ns 1.294ns 0.918ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns - " "Info: - Micro clock to output delay of source is 0.376 ns" {  } { { "lcd.v" "" { Text "D:/lcd_1602/lcd.v" 84 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.485 ns - Shortest register register " "Info: - Shortest register to register delay is 1.485 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lcd:inst\|clk_int 1 REG LC_X12_Y3_N2 37 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y3_N2; Fanout = 37; REG Node = 'lcd:inst\|clk_int'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_1602" "UNKNOWN" "V1" "D:/lcd_1602/db/lcd_1602.quartus_db" { Floorplan "D:/lcd_1602/" "" "" { lcd:inst|clk_int } "NODE_NAME" } "" } } { "lcd.v" "" { Text "D:/lcd_1602/lcd.v" 84 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.894 ns) + CELL(0.591 ns) 1.485 ns lcd:inst\|clk_int 2 REG LC_X12_Y3_N2 37 " "Info: 2: + IC(0.894 ns) + CELL(0.591 ns) = 1.485 ns; Loc. = LC_X12_Y3_N2; Fanout = 37; REG Node = 'lcd:inst\|clk_int'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_1602" "UNKNOWN" "V1" "D:/lcd_1602/db/lcd_1602.quartus_db" { Floorplan "D:/lcd_1602/" "" "1.485 ns" { lcd:inst|clk_int lcd:inst|clk_int } "NODE_NAME" } "" } } { "lcd.v" "" { Text "D:/lcd_1602/lcd.v" 84 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.591 ns ( 39.80 % ) " "Info: Total cell delay = 0.591 ns ( 39.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.894 ns ( 60.20 % ) " "Info: Total interconnect delay = 0.894 ns ( 60.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_1602" "UNKNOWN" "V1" "D:/lcd_1602/db/lcd_1602.quartus_db" { Floorplan "D:/lcd_1602/" "" "1.485 ns" { lcd:inst|clk_int lcd:inst|clk_int } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "1.485 ns" { lcd:inst|clk_int lcd:inst|clk_int } { 0.000ns 0.894ns } { 0.000ns 0.591ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "lcd.v" "" { Text "D:/lcd_1602/lcd.v" 84 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_1602" "UNKNOWN" "V1" "D:/lcd_1602/db/lcd_1602.quartus_db" { Floorplan "D:/lcd_1602/" "" "19.063 ns" { clk lcd:inst|clkcnt[14] lcd:inst|Equal~337 lcd:inst|Equal~338 lcd:inst|Equal~340 lcd:inst|clkdiv lcd:inst|clk_int } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "19.063 ns" { clk clk~combout lcd:inst|clkcnt[14] lcd:inst|Equal~337 lcd:inst|Equal~338 lcd:inst|Equal~340 lcd:inst|clkdiv lcd:inst|clk_int } { 0.000ns 0.000ns 1.738ns 1.245ns 1.817ns 1.688ns 0.689ns 4.878ns } { 0.000ns 1.163ns 1.294ns 0.914ns 0.914ns 0.511ns 1.294ns 0.918ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_1602" "UNKNOWN" "V1" "D:/lcd_1602/db/lcd_1602.quartus_db" { Floorplan "D:/lcd_1602/" "" "13.617 ns" { clk lcd:inst|clkcnt[18] lcd:inst|Equal~339 lcd:inst|Equal~340 lcd:inst|clkdiv lcd:inst|clk_int } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "13.617 ns" { clk clk~combout lcd:inst|clkcnt[18] lcd:inst|Equal~339 lcd:inst|Equal~340 lcd:inst|clkdiv lcd:inst|clk_int } { 0.000ns 0.000ns 1.738ns 0.938ns 0.305ns 0.689ns 4.878ns } { 0.000ns 1.163ns 1.294ns 0.200ns 0.200ns 1.294ns 0.918ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_1602" "UNKNOWN" "V1" "D:/lcd_1602/db/lcd_1602.quartus_db" { Floorplan "D:/lcd_1602/" "" "1.485 ns" { lcd:inst|clk_int lcd:inst|clk_int } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "1.485 ns" { lcd:inst|clk_int lcd:inst|clk_int } { 0.000ns 0.894ns } { 0.000ns 0.591ns } } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "lcd:inst\|clkcnt\[20\] reset clk 4.019 ns register " "Info: tsu for register \"lcd:inst\|clkcnt\[20\]\" (data pin = \"reset\", clock pin = \"clk\") is 4.019 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.505 ns + Longest pin register " "Info: + Longest pin to register delay is 7.505 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns reset 1 PIN PIN_93 40 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_93; Fanout = 40; PIN Node = 'reset'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_1602" "UNKNOWN" "V1" "D:/lcd_1602/db/lcd_1602.quartus_db" { Floorplan "D:/lcd_1602/" "" "" { reset } "NODE_NAME" } "" } } { "lcd_1602.bdf" "" { Schematic "D:/lcd_1602/lcd_1602.bdf" { { 64 64 232 80 "reset" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.319 ns) + CELL(0.740 ns) 4.191 ns lcd:inst\|clkcnt\[3\]~497 2 COMB LC_X14_Y6_N1 21 " "Info: 2: + IC(2.319 ns) + CELL(0.740 ns) = 4.191 ns; Loc. = LC_X14_Y6_N1; Fanout = 21; COMB Node = 'lcd:inst\|clkcnt\[3\]~497'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_1602" "UNKNOWN" "V1" "D:/lcd_1602/db/lcd_1602.quartus_db" { Floorplan "D:/lcd_1602/" "" "3.059 ns" { reset lcd:inst|clkcnt[3]~497 } "NODE_NAME" } "" } } { "lcd.v" "" { Text "D:/lcd_1602/lcd.v" 64 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.554 ns) + CELL(1.760 ns) 7.505 ns lcd:inst\|clkcnt\[20\] 3 REG LC_X16_Y6_N5 3 " "Info: 3: + IC(1.554 ns) + CELL(1.760 ns) = 7.505 ns; Loc. = LC_X16_Y6_N5; Fanout = 3; REG Node = 'lcd:inst\|clkcnt\[20\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_1602" "UNKNOWN" "V1" "D:/lcd_1602/db/lcd_1602.quartus_db" { Floorplan "D:/lcd_1602/" "" "3.314 ns" { lcd:inst|clkcnt[3]~497 lcd:inst|clkcnt[20] } "NODE_NAME" } "" } } { "lcd.v" "" { Text "D:/lcd_1602/lcd.v" 64 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.632 ns ( 48.39 % ) " "Info: Total cell delay = 3.632 ns ( 48.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.873 ns ( 51.61 % ) " "Info: Total interconnect delay = 3.873 ns ( 51.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_1602" "UNKNOWN" "V1" "D:/lcd_1602/db/lcd_1602.quartus_db" { Floorplan "D:/lcd_1602/" "" "7.505 ns" { reset lcd:inst|clkcnt[3]~497 lcd:inst|clkcnt[20] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.505 ns" { reset reset~combout lcd:inst|clkcnt[3]~497 lcd:inst|clkcnt[20] } { 0.000ns 0.000ns 2.319ns 1.554ns } { 0.000ns 1.132ns 0.740ns 1.760ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "lcd.v" "" { Text "D:/lcd_1602/lcd.v" 64 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.819 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 21 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 21; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_1602" "UNKNOWN" "V1" "D:/lcd_1602/db/lcd_1602.quartus_db" { Floorplan "D:/lcd_1602/" "" "" { clk } "NODE_NAME" } "" } } { "lcd_1602.bdf" "" { Schematic "D:/lcd_1602/lcd_1602.bdf" { { 48 64 232 64 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(0.918 ns) 3.819 ns lcd:inst\|clkcnt\[20\] 2 REG LC_X16_Y6_N5 3 " "Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X16_Y6_N5; Fanout = 3; REG Node = 'lcd:inst\|clkcnt\[20\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_1602" "UNKNOWN" "V1" "D:/lcd_1602/db/lcd_1602.quartus_db" { Floorplan "D:/lcd_1602/" "" "2.656 ns" { clk lcd:inst|clkcnt[20] } "NODE_NAME" } "" } } { "lcd.v" "" { Text "D:/lcd_1602/lcd.v" 64 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 54.49 % ) " "Info: Total cell delay = 2.081 ns ( 54.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.738 ns ( 45.51 % ) " "Info: Total interconnect delay = 1.738 ns ( 45.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_1602" "UNKNOWN" "V1" "D:/lcd_1602/db/lcd_1602.quartus_db" { Floorplan "D:/lcd_1602/" "" "3.819 ns" { clk lcd:inst|clkcnt[20] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout lcd:inst|clkcnt[20] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_1602" "UNKNOWN" "V1" "D:/lcd_1602/db/lcd_1602.quartus_db" { Floorplan "D:/lcd_1602/" "" "7.505 ns" { reset lcd:inst|clkcnt[3]~497 lcd:inst|clkcnt[20] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.505 ns" { reset reset~combout lcd:inst|clkcnt[3]~497 lcd:inst|clkcnt[20] } { 0.000ns 0.000ns 2.319ns 1.554ns } { 0.000ns 1.132ns 0.740ns 1.760ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_1602" "UNKNOWN" "V1" "D:/lcd_1602/db/lcd_1602.quartus_db" { Floorplan "D:/lcd_1602/" "" "3.819 ns" { clk lcd:inst|clkcnt[20] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout lcd:inst|clkcnt[20] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk lcd_data\[6\] lcd:inst\|data\[6\] 28.145 ns register " "Info: tco from clock \"clk\" to destination pin \"lcd_data\[6\]\" through register \"lcd:inst\|data\[6\]\" is 28.145 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 23.385 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 23.385 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 21 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 21; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_1602" "UNKNOWN" "V1" "D:/lcd_1602/db/lcd_1602.quartus_db" { Floorplan "D:/lcd_1602/" "" "" { clk } "NODE_NAME" } "" } } { "lcd_1602.bdf" "" { Schematic "D:/lcd_1602/lcd_1602.bdf" { { 48 64 232 64 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns lcd:inst\|clkcnt\[14\] 2 REG LC_X15_Y6_N9 3 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X15_Y6_N9; Fanout = 3; REG Node = 'lcd:inst\|clkcnt\[14\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_1602" "UNKNOWN" "V1" "D:/lcd_1602/db/lcd_1602.quartus_db" { Floorplan "D:/lcd_1602/" "" "3.032 ns" { clk lcd:inst|clkcnt[14] } "NODE_NAME" } "" } } { "lcd.v" "" { Text "D:/lcd_1602/lcd.v" 64 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.245 ns) + CELL(0.914 ns) 6.354 ns lcd:inst\|Equal~337 3 COMB LC_X16_Y6_N9 1 " "Info: 3: + IC(1.245 ns) + CELL(0.914 ns) = 6.354 ns; Loc. = LC_X16_Y6_N9; Fanout = 1; COMB Node = 'lcd:inst\|Equal~337'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_1602" "UNKNOWN" "V1" "D:/lcd_1602/db/lcd_1602.quartus_db" { Floorplan "D:/lcd_1602/" "" "2.159 ns" { lcd:inst|clkcnt[14] lcd:inst|Equal~337 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.817 ns) + CELL(0.914 ns) 9.085 ns lcd:inst\|Equal~338 4 COMB LC_X14_Y6_N3 2 " "Info: 4: + IC(1.817 ns) + CELL(0.914 ns) = 9.085 ns; Loc. = LC_X14_Y6_N3; Fanout = 2; COMB Node = 'lcd:inst\|Equal~338'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_1602" "UNKNOWN" "V1" "D:/lcd_1602/db/lcd_1602.quartus_db" { Floorplan "D:/lcd_1602/" "" "2.731 ns" { lcd:inst|Equal~337 lcd:inst|Equal~338 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.688 ns) + CELL(0.511 ns) 11.284 ns lcd:inst\|Equal~340 5 COMB LC_X16_Y6_N8 1 " "Info: 5: + IC(1.688 ns) + CELL(0.511 ns) = 11.284 ns; Loc. = LC_X16_Y6_N8; Fanout = 1; COMB Node = 'lcd:inst\|Equal~340'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_1602" "UNKNOWN" "V1" "D:/lcd_1602/db/lcd_1602.quartus_db" { Floorplan "D:/lcd_1602/" "" "2.199 ns" { lcd:inst|Equal~338 lcd:inst|Equal~340 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.689 ns) + CELL(1.294 ns) 13.267 ns lcd:inst\|clkdiv 6 REG LC_X16_Y6_N6 3 " "Info: 6: + IC(0.689 ns) + CELL(1.294 ns) = 13.267 ns; Loc. = LC_X16_Y6_N6; Fanout = 3; REG Node = 'lcd:inst\|clkdiv'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_1602" "UNKNOWN" "V1" "D:/lcd_1602/db/lcd_1602.quartus_db" { Floorplan "D:/lcd_1602/" "" "1.983 ns" { lcd:inst|Equal~340 lcd:inst|clkdiv } "NODE_NAME" } "" } } { "lcd.v" "" { Text "D:/lcd_1602/lcd.v" 77 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.878 ns) + CELL(1.294 ns) 19.439 ns lcd:inst\|clk_int 7 REG LC_X12_Y3_N2 37 " "Info: 7: + IC(4.878 ns) + CELL(1.294 ns) = 19.439 ns; Loc. = LC_X12_Y3_N2; Fanout = 37; REG Node = 'lcd:inst\|clk_int'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/