lcd_1602.tan.qmsg

Verilog 经典实例

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "29 " "Warning: Found 29 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[19\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[19\]\" as buffer" {  } { { "lcd.v" "" { Text "D:/lcd_1602/lcd.v" 64 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[19\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[18\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[18\]\" as buffer" {  } { { "lcd.v" "" { Text "D:/lcd_1602/lcd.v" 64 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[18\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[16\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[16\]\" as buffer" {  } { { "lcd.v" "" { Text "D:/lcd_1602/lcd.v" 64 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[16\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[17\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[17\]\" as buffer" {  } { { "lcd.v" "" { Text "D:/lcd_1602/lcd.v" 64 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[17\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "lcd:inst\|Equal~337 " "Info: Detected gated clock \"lcd:inst\|Equal~337\" as buffer" {  } { { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|Equal~337" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[15\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[15\]\" as buffer" {  } { { "lcd.v" "" { Text "D:/lcd_1602/lcd.v" 64 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[15\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[14\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[14\]\" as buffer" {  } { { "lcd.v" "" { Text "D:/lcd_1602/lcd.v" 64 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[14\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[13\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[13\]\" as buffer" {  } { { "lcd.v" "" { Text "D:/lcd_1602/lcd.v" 64 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[13\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[12\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[12\]\" as buffer" {  } { { "lcd.v" "" { Text "D:/lcd_1602/lcd.v" 64 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[12\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "lcd:inst\|Equal~336 " "Info: Detected gated clock \"lcd:inst\|Equal~336\" as buffer" {  } { { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|Equal~336" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[10\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[10\]\" as buffer" {  } { { "lcd.v" "" { Text "D:/lcd_1602/lcd.v" 64 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[10\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[11\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[11\]\" as buffer" {  } { { "lcd.v" "" { Text "D:/lcd_1602/lcd.v" 64 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[11\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[9\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[9\]\" as buffer" {  } { { "lcd.v" "" { Text "D:/lcd_1602/lcd.v" 64 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[9\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[8\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[8\]\" as buffer" {  } { { "lcd.v" "" { Text "D:/lcd_1602/lcd.v" 64 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[8\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "lcd:inst\|Equal~335 " "Info: Detected gated clock \"lcd:inst\|Equal~335\" as buffer" {  } { { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|Equal~335" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[7\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[7\]\" as buffer" {  } { { "lcd.v" "" { Text "D:/lcd_1602/lcd.v" 64 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[7\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[6\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[6\]\" as buffer" {  } { { "lcd.v" "" { Text "D:/lcd_1602/lcd.v" 64 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[6\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[5\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[5\]\" as buffer" {  } { { "lcd.v" "" { Text "D:/lcd_1602/lcd.v" 64 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[5\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[4\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[4\]\" as buffer" {  } { { "lcd.v" "" { Text "D:/lcd_1602/lcd.v" 64 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[4\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "lcd:inst\|Equal~334 " "Info: Detected gated clock \"lcd:inst\|Equal~334\" as buffer" {  } { { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|Equal~334" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[3\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[3\]\" as buffer" {  } { { "lcd.v" "" { Text "D:/lcd_1602/lcd.v" 64 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[2\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[2\]\" as buffer" {  } { { "lcd.v" "" { Text "D:/lcd_1602/lcd.v" 64 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[1\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[1\]\" as buffer" {  } { { "lcd.v" "" { Text "D:/lcd_1602/lcd.v" 64 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "lcd:inst\|Equal~339 " "Info: Detected gated clock \"lcd:inst\|Equal~339\" as buffer" {  } { { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|Equal~339" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[0\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[0\]\" as buffer" {  } { { "lcd.v" "" { Text "D:/lcd_1602/lcd.v" 64 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[20\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[20\]\" as buffer" {  } { { "lcd.v" "" { Text "D:/lcd_1602/lcd.v" 64 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[20\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "lcd:inst\|Equal~340 " "Info: Detected gated clock \"lcd:inst\|Equal~340\" as buffer" {  } { { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|Equal~340" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clk_int " "Info: Detected ripple clock \"lcd:inst\|clk_int\" as buffer" {  } { { "lcd.v" "" { Text "D:/lcd_1602/lcd.v" 84 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clk_int" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkdiv " "Info: Detected ripple clock \"lcd:inst\|clkdiv\" as buffer" {  } { { "lcd.v" "" { Text "D:/lcd_1602/lcd.v" 77 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkdiv" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register lcd:inst\|counter\[2\] register lcd:inst\|address\[2\] 68.7 MHz 14.555 ns Internal " "Info: Clock \"clk\" has Internal fmax of 68.7 MHz between source register \"lcd:inst\|counter\[2\]\" and destination register \"lcd:inst\|address\[2\]\" (period= 14.555 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.400 ns + Longest register register " "Info: + Longest register to register delay is 8.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lcd:inst\|counter\[2\] 1 REG LC_X7_Y8_N6 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y8_N6; Fanout = 11; REG Node = 'lcd:inst\|counter\[2\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_1602" "UNKNOWN" "V1" "D:/lcd_1602/db/lcd_1602.quartus_db" { Floorplan "D:/lcd_1602/" "" "" { lcd:inst|counter[2] } "NODE_NAME" } "" } } { "lcd.v" "" { Text "D:/lcd_1602/lcd.v" 100 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.926 ns) + CELL(0.914 ns) 1.840 ns lcd:inst\|Equal~332 2 COMB LC_X7_Y8_N8 2 " "Info: 2: + IC(0.926 ns) + CELL(0.914 ns) = 1.840 ns; Loc. = LC_X7_Y8_N8; Fanout = 2; COMB Node = 'lcd:inst\|Equal~332'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_1602" "UNKNOWN" "V1" "D:/lcd_1602/db/lcd_1602.quartus_db" { Floorplan "D:/lcd_1602/" "" "1.840 ns" { lcd:inst|counter[2] lcd:inst|Equal~332 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 2.345 ns lcd:inst\|LessThan~405 3 COMB LC_X7_Y8_N9 5 " "Info: 3: + IC(0.305 ns) + CELL(0.200 ns) = 2.345 ns; Loc. = LC_X7_Y8_N9; Fanout = 5; COMB Node = 'lcd:inst\|LessThan~405'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_1602" "UNKNOWN" "V1" "D:/lcd_1602/db/lcd_1602.quartus_db" { Floorplan "D:/lcd_1602/" "" "0.505 ns" { lcd:inst|Equal~332 lcd:inst|LessThan~405 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.990 ns) + CELL(0.511 ns) 4.846 ns lcd:inst\|Select~1824 4 COMB LC_X5_Y8_N2 1 " "Info: 4: + IC(1.990 ns) + CELL(0.511 ns) = 4.846 ns; Loc. = LC_X5_Y8_N2; Fanout = 1; COMB Node = 'lcd:inst\|Select~1824'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_1602" "UNKNOWN" "V1" "D:/lcd_1602/db/lcd_1602.quartus_db" { Floorplan "D:/lcd_1602/" "" "2.501 ns" { lcd:inst|LessThan~405 lcd:inst|Select~1824 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 5.351 ns lcd:inst\|Select~1825 5 COMB LC_X5_Y8_N3 7 " "Info: 5: + IC(0.305 ns) + CELL(0.200 ns) = 5.351 ns; Loc. = LC_X5_Y8_N3; Fanout = 7; COMB Node = 'lcd:inst\|Select~1825'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_1602" "UNKNOWN" "V1" "D:/lcd_1602/db/lcd_1602.quartus_db" { Floorplan "D:/lcd_1602/" "" "0.505 ns" { lcd:inst|Select~1824 lcd:inst|Select~1825 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.806 ns) + CELL(1.243 ns) 8.400 ns lcd:inst\|address\[2\] 6 REG LC_X5_Y9_N5 10 " "Info: 6: + IC(1.806 ns) + CELL(1.243 ns) = 8.400 ns; Loc. = LC_X5_Y9_N5; Fanout = 10; REG Node = 'lcd:inst\|address\[2\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_1602" "UNKNOWN" "V1" "D:/lcd_1602/db/lcd_1602.quartus_db" { Floorplan "D:/lcd_1602/" "" "3.049 ns" { lcd:inst|Select~1825 lcd:inst|address[2] } "NODE_NAME" } "" } } { "lcd.v" "" { Text "D:/lcd_1602/lcd.v" 100 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.068 ns ( 36.52 % ) " "Info: Total cell delay = 3.068 ns ( 36.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.332 ns ( 63.48 % ) " "Info: Total interconnect delay = 5.332 ns ( 63.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_1602" "UNKNOWN" "V1" "D:/lcd_1602/db/lcd_1602.quartus_db" { Floorplan "D:/lcd_1602/" "" "8.400 ns" { lcd:inst|counter[2] lcd:inst|Equal~332 lcd:inst|LessThan~405 lcd:inst|Select~1824 lcd:inst|Select~1825 lcd:inst|address[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "8.400 ns" { lcd:inst|counter[2] lcd:inst|Equal~332 lcd:inst|LessThan~405 lcd:inst|Select~1824 lcd:inst|Select~1825 lcd:inst|address[2] } { 0.000ns 0.926ns 0.305ns 1.990ns 0.305ns 1.806ns } { 0.000ns 0.914ns 0.200ns 0.511ns 0.200ns 1.243ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-5.446 ns - Smallest " "Info: - Smallest clock skew is -5.446 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 17.939 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 17.939 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 21 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 21; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_1602" "UNKNOWN" "V1" "D:/lcd_1602/db/lcd_1602.quartus_db" { Floorplan "D:/lcd_1602/" "" "" { clk } "NODE_NAME" } "" } } { "lcd_1602.bdf" "" { Schematic "D:/lcd_1602/lcd_1602.bdf" { { 48 64 232 64 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns lcd:inst\|clkcnt\[18\] 2 REG LC_X16_Y6_N3 4 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X16_Y6_N3; Fanout = 4; REG Node = 'lcd:inst\|clkcnt\[18\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_1602" "UNKNOWN" "V1" "D:/lcd_1602/db/lcd_1602.quartus_db" { Floorplan "D:/lcd_1602/" "" "3.032 ns" { clk lcd:inst|clkcnt[18] } "NODE_NAME" } "" } } { "lcd.v" "" { Text "D:/lcd_1602/lcd.v" 64 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.938 ns) + CELL(0.200 ns) 5.333 ns lcd:inst\|Equal~339 3 COMB LC_X16_Y6_N7 2 " "Info: 3: + IC(0.938 ns) + CELL(0.200 ns) = 5.333 ns; Loc. = LC_X16_Y6_N7; Fanout = 2; COMB Node = 'lcd:inst\|Equal~339'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_1602" "UNKNOWN" "V1" "D:/lcd_1602/db/lcd_1602.quartus_db" { Floorplan "D:/lcd_1602/" "" "1.138 ns" { lcd:inst|clkcnt[18] lcd:inst|Equal~339 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 5.838 ns lcd:inst\|Equal~340 4 COMB LC_X16_Y6_N8 1 " "Info: 4: + IC(0.305 ns) + CELL(0.200 ns) = 5.838 ns; Loc. = LC_X16_Y6_N8; Fanout = 1; COMB Node = 'lcd:inst\|Equal~340'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_1602" "UNKNOWN" "V1" "D:/lcd_1602/db/lcd_1602.quartus_db" { Floorplan "D:/lcd_1602/" "" "0.505 ns" { lcd:inst|Equal~339 lcd:inst|Equal~340 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.689 ns) + CELL(1.294 ns) 7.821 ns lcd:inst\|clkdiv 5 REG LC_X16_Y6_N6 3 " "Info: 5: + IC(0.689 ns) + CELL(1.294 ns) = 7.821 ns; Loc. = LC_X16_Y6_N6; Fanout = 3; REG Node = 'lcd:inst\|clkdiv'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_1602" "UNKNOWN" "V1" "D:/lcd_1602/db/lcd_1602.quartus_db" { Floorplan "D:/lcd_1602/" "" "1.983 ns" { lcd:inst|Equal~340 lcd:inst|clkdiv } "NODE_NAME" } "" } } { "lcd.v" "" { Text "D:/lcd_1602/lcd.v" 77 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.878 ns) + CELL(1.294 ns) 13.993 ns lcd:inst\|clk_int 6 REG LC_X12_Y3_N2 37 " "Info: 6: + IC(4.878 ns) + CELL(1.294 ns) = 13.993 ns; Loc. = LC_X12_Y3_N2; Fanout = 37; REG Node = 'lcd:inst\|clk_int'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_1602" "UNKNOWN" "V1" "D:/lcd_1602/db/lcd_1602.quartus_db" { Floorplan "D:/lcd_1602/" "" "6.172 ns" { lcd:inst|clkdiv lcd:inst|clk_int } "NODE_NAME" } "" } } { "lcd.v" "" { Text "D:/lcd_1602/lcd.v" 84 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.028 ns) + CELL(0.918 ns) 17.939 ns lcd:inst\|address\[2\] 7 REG LC_X5_Y9_N5 10 " "Info: 7: + IC(3.028 ns) + CELL(0.918 ns) = 17.939 ns; Loc. = LC_X5_Y9_N5; Fanout = 10; REG Node = 'lcd:inst\|address\[2\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_1602" "UNKNOWN" "V1" "D:/lcd_1602/db/lcd_1602.quartus_db" { Floorplan "D:/lcd_1602/" "" "3.946 ns" { lcd:inst|clk_int lcd:inst|address[2] } "NODE_NAME" } "" } } { "lcd.v" "" { Text "D:/lcd_1602/lcd.v" 100 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.363 ns ( 35.47 % ) " "Info: Total cell delay = 6.363 ns ( 35.47 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "11.576 ns ( 64.53 % ) " "Info: Total interconnect delay = 11.576 ns ( 64.53 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_1602" "UNKNOWN" "V1" "D:/lcd_1602/db/lcd_1602.quartus_db" { Floorplan "D:/lcd_1602/" "" "17.939 ns" { clk lcd:inst|clkcnt[18] lcd:inst|Equal~339 lcd:inst|Equal~340 lcd:inst|clkdiv lcd:inst|clk_int lcd:inst|address[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "17.939 ns" { clk clk~combout lcd:inst|clkcnt[18] lcd:inst|Equal~339 lcd:inst|Equal~340 lcd:inst|clkdiv lcd:inst|clk_int lcd:inst|address[2] } { 0.000ns 0.000ns 1.738ns 0.938ns 0.305ns 0.689ns 4.878ns 3.028ns } { 0.000ns 1.163ns 1.294ns 0.200ns 0.200ns 1.294ns 1.294ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 23.385 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 23.385 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 21 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 21; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_1602" "UNKNOWN" "V1" "D:/lcd_1602/db/lcd_1602.quartus_db" { Floorplan "D:/lcd_1602/" "" "" { clk } "NODE_NAME" } "" } } { "lcd_1602.bdf" "" { Schematic "D:/lcd_1602/lcd_1602.bdf" { { 48 64 232 64 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns lcd:inst\|clkcnt\[14\] 2 REG LC_X15_Y6_N9 3 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X15_Y6_N9; Fanout = 3; REG Node = 'lcd:inst\|clkcnt\[14\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_1602" "UNKNOWN" "V1" "D:/lcd_1602/db/lcd_1602.quartus_db" { Floorplan "D:/lcd_1602/" "" "3.032 ns" { clk lcd:inst|clkcnt[14] } "NODE_NAME" } "" } } { "lcd.v" "" { Text "D:/lcd_1602/lcd.v" 64 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.245 ns) + CELL(0.914 ns) 6.354 ns lcd:inst\|Equal~337 3 COMB LC_X16_Y6_N9 1 " "Info: 3: + IC(1.245 ns) + CELL(0.914 ns) = 6.354 ns; Loc. = LC_X16_Y6_N9; Fanout = 1; COMB Node = 'lcd:inst\|Equal~337'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_1602" "UNKNOWN" "V1" "D:/lcd_1602/db/lcd_1602.quartus_db" { Floorplan "D:/lcd_1602/" "" "2.159 ns" { lcd:inst|clkcnt[14] lcd:inst|Equal~337 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.817 ns) + CELL(0.914 ns) 9.085 ns lcd:inst\|Equal~338 4 COMB LC_X14_Y6_N3 2 " "Info: 4: + IC(1.817 ns) + CELL(0.914 ns) = 9.085 ns; Loc. = LC_X14_Y6_N3; Fanout = 2; COMB Node = 'lcd:inst\|Equal~338'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_1602" "UNKNOWN" "V1" "D:/lcd_1602/db/lcd_1602.quartus_db" { Floorplan "D:/lcd_1602/" "" "2.731 ns" { lcd:inst|Equal~337 lcd:inst|Equal~338 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.688 ns) + CELL(0.511 ns) 11.284 ns lcd:inst\|Equal~340 5 COMB LC_X16_Y6_N8 1 " "Info: 5: + IC(1.688 ns) + CELL(0.511 ns) = 11.284 ns; Loc. = LC_X16_Y6_N8; Fanout = 1; COMB Node = 'lcd:inst\|Equal~340'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_1602" "UNKNOWN" "V1" "D:/lcd_1602/db/lcd_1602.quartus_db" { Floorplan "D:/lcd_1602/" "" "2.199 ns" { lcd:inst|Equal~338 lcd:inst|Equal~340 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.689 ns) + CELL(1.294 ns) 13.267 ns lcd:inst\|clkdiv 6 REG LC_X16_Y6_N6 3 " "Info: 6: + IC(0.689 ns) + CELL(1.294 ns) = 13.267 ns; Loc. = LC_X16_Y6_N6; Fanout = 3; REG Node = 'lcd:inst\|clkdiv'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_1602" "UNKNOWN" "V1" "D:/lcd_1602/db/lcd_1602.quartus_db" { Floorplan "D:/lcd_1602/" "" "1.983 ns" { lcd:inst|Equal~340 lcd:inst|clkdiv } "NODE_NAME" } "" } } { "lcd.v" "" { Text "D:/lcd_1602/lcd.v" 77 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.878 ns) + CELL(1.294 ns) 19.439 ns lcd:inst\|clk_int 7 REG LC_X12_Y3_N2 37 " "Info: 7: + IC(4.878 ns) + CELL(1.294 ns) = 19.439 ns; Loc. = LC_X12_Y3_N2; Fanout = 37; REG Node = 'lcd:inst\|clk_int'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_1602" "UNKNOWN" "V1" "D:/lcd_1602/db/lcd_1602.quartus_db" { Floorplan "D:/lcd_1602/" "" "6.172 ns" { lcd:inst|clkdiv lcd:inst|clk_int } "NODE_NAME" } "" } } { "lcd.v" "" { Text "D:/lcd_1602/lcd.v" 84 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.028 ns) + CELL(0.918 ns) 23.385 ns lcd:inst\|counter\[2\] 8 REG LC_X7_Y8_N6 11 " "Info: 8: + IC(3.028 ns) + CELL(0.918 ns) = 23.385 ns; Loc. = LC_X7_Y8_N6; Fanout = 11; REG Node = 'lcd:inst\|counter\[2\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_1602" "UNKNOWN" "V1" "D:/lcd_1602/db/lcd_1602.quartus_db" { Floorplan "D:/lcd_1602/" "" "3.946 ns" { lcd:inst|clk_int lcd:inst|counter[2] } "NODE_NAME" } "" } } { "lcd.v" "" { Text "D:/lcd_1602/lcd.v" 100 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.302 ns ( 35.50 % ) " "Info: Total cell delay = 8.302 ns ( 35.50 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "15.083 ns ( 64.50 % ) " "Info: Total interconnect delay = 15.083 ns ( 64.50 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_1602" "UNKNOWN" "V1" "D:/lcd_1602/db/lcd_1602.quartus_db" { Floorplan "D:/lcd_1602/" "" "23.385 ns" { clk lcd:inst|clkcnt[14] lcd:inst|Equal~337 lcd:inst|Equal~338 lcd:inst|Equal~340 lcd:inst|clkdiv lcd:inst|clk_int lcd:inst|counter[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "23.385 ns" { clk clk~combout lcd:inst|clkcnt[14] lcd:inst|Equal~337 lcd:inst|Equal~338 lcd:inst|Equal~340 lcd:inst|clkdiv lcd:inst|clk_int lcd:inst|counter[2] } { 0.000ns 0.000ns 1.738ns 1.245ns 1.817ns 1.688ns 0.689ns 4.878ns 3.028ns } { 0.000ns 1.163ns 1.294ns 0.914ns 0.914ns 0.511ns 1.294ns 1.294ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_1602" "UNKNOWN" "V1" "D:/lcd_1602/db/lcd_1602.quartus_db" { Floorplan "D:/lcd_1602/" "" "17.939 ns" { clk lcd:inst|clkcnt[18] lcd:inst|Equal~339 lcd:inst|Equal~340 lcd:inst|clkdiv lcd:inst|clk_int lcd:inst|address[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "17.939 ns" { clk clk~combout lcd:inst|clkcnt[18] lcd:inst|Equal~339 lcd:inst|Equal~340 lcd:inst|clkdiv lcd:inst|clk_int lcd:inst|address[2] } { 0.000ns 0.000ns 1.738ns 0.938ns 0.305ns 0.689ns 4.878ns 3.028ns } { 0.000ns 1.163ns 1.294ns 0.200ns 0.200ns 1.294ns 1.294ns 0.918ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_1602" "UNKNOWN" "V1" "D:/lcd_1602/db/lcd_1602.quartus_db" { Floorplan "D:/lcd_1602/" "" "23.385 ns" { clk lcd:inst|clkcnt[14] lcd:inst|Equal~337 lcd:inst|Equal~338 lcd:inst|Equal~340 lcd:inst|clkdiv lcd:inst|clk_int lcd:inst|counter[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "23.385 ns" { clk clk~combout lcd:inst|clkcnt[14] lcd:inst|Equal~337 lcd:inst|Equal~338 lcd:inst|Equal~340 lcd:inst|clkdiv lcd:inst|clk_int lcd:inst|counter[2] } { 0.000ns 0.000ns 1.738ns 1.245ns 1.817ns 1.688ns 0.689ns 4.878ns 3.028ns } { 0.000ns 1.163ns 1.294ns 0.914ns 0.914ns 0.511ns 1.294ns 1.294ns 0.918ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "lcd.v" "" { Text "D:/lcd_1602/lcd.v" 100 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "lcd.v" "" { Text "D:/lcd_1602/lcd.v" 100 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_1602" "UNKNOWN" "V1" "D:/lcd_1602/db/lcd_1602.quartus_db" { Floorplan "D:/lcd_1602/" "" "8.400 ns" { lcd:inst|counter[2] lcd:inst|Equal~332 lcd:inst|LessThan~405 lcd:inst|Select~1824 lcd:inst|Select~1825 lcd:inst|address[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "8.400 ns" { lcd:inst|counter[2] lcd:inst|Equal~332 lcd:inst|LessThan~405 lcd:inst|Select~1824 lcd:inst|Select~1825 lcd:inst|address[2] } { 0.000ns 0.926ns 0.305ns 1.990ns 0.305ns 1.806ns } { 0.000ns 0.914ns 0.200ns 0.511ns 0.200ns 1.243ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_1602" "UNKNOWN" "V1" "D:/lcd_1602/db/lcd_1602.quartus_db" { Floorplan "D:/lcd_1602/" "" "17.939 ns" { clk lcd:inst|clkcnt[18] lcd:inst|Equal~339 lcd:inst|Equal~340 lcd:inst|clkdiv lcd:inst|clk_int lcd:inst|address[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "17.939 ns" { clk clk~combout lcd:inst|clkcnt[18] lcd:inst|Equal~339 lcd:inst|Equal~340 lcd:inst|clkdiv lcd:inst|clk_int lcd:inst|address[2] } { 0.000ns 0.000ns 1.738ns 0.938ns 0.305ns 0.689ns 4.878ns 3.028ns } { 0.000ns 1.163ns 1.294ns 0.200ns 0.200ns 1.294ns 1.294ns 0.918ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_1602" "UNKNOWN" "V1" "D:/lcd_1602/db/lcd_1602.quartus_db" { Floorplan "D:/lcd_1602/" "" "23.385 ns" { clk lcd:inst|clkcnt[14] lcd:inst|Equal~337 lcd:inst|Equal~338 lcd:inst|Equal~340 lcd:inst|clkdiv lcd:inst|clk_int lcd:inst|counter[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "23.385 ns" { clk clk~combout lcd:inst|clkcnt[14] lcd:inst|Equal~337 lcd:inst|Equal~338 lcd:inst|Equal~340 lcd:inst|clkdiv lcd:inst|clk_int lcd:inst|counter[2] } { 0.000ns 0.000ns 1.738ns 1.245ns 1.817ns 1.688ns 0.689ns 4.878ns 3.028ns } { 0.000ns 1.163ns 1.294ns 0.914ns 0.914ns 0.511ns 1.294ns 1.294ns 0.918ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 183 " "Warning: Circuit may not operate. Detected 183 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}