ps2.tan.qmsg

Verilog 经典实例

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "PS2.bdf" "" { Schematic "D:/Verilog_PS2_1c12/PS2.bdf" { { 360 -128 40 376 "clk" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "30 " "Warning: Found 30 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "convert:inst1\|reduce_or~1306 " "Info: Detected gated clock \"convert:inst1\|reduce_or~1306\" as buffer" {  } { { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "convert:inst1\|reduce_or~1306" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "convert:inst1\|reduce_or~1305 " "Info: Detected gated clock \"convert:inst1\|reduce_or~1305\" as buffer" {  } { { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "convert:inst1\|reduce_or~1305" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "convert:inst1\|reduce_or~1304 " "Info: Detected gated clock \"convert:inst1\|reduce_or~1304\" as buffer" {  } { { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "convert:inst1\|reduce_or~1304" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "convert:inst1\|reduce_or~1303 " "Info: Detected gated clock \"convert:inst1\|reduce_or~1303\" as buffer" {  } { { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "convert:inst1\|reduce_or~1303" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "convert:inst1\|Select~12061 " "Info: Detected gated clock \"convert:inst1\|Select~12061\" as buffer" {  } { { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "convert:inst1\|Select~12061" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "convert:inst1\|Select~12060 " "Info: Detected gated clock \"convert:inst1\|Select~12060\" as buffer" {  } { { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "convert:inst1\|Select~12060" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "convert:inst1\|reduce_or~1300 " "Info: Detected gated clock \"convert:inst1\|reduce_or~1300\" as buffer" {  } { { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "convert:inst1\|reduce_or~1300" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "convert:inst1\|reduce_or~1299 " "Info: Detected gated clock \"convert:inst1\|reduce_or~1299\" as buffer" {  } { { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "convert:inst1\|reduce_or~1299" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "convert:inst1\|reduce_or~1298 " "Info: Detected gated clock \"convert:inst1\|reduce_or~1298\" as buffer" {  } { { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "convert:inst1\|reduce_or~1298" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "data_scanC:inst\|tmp\[8\] " "Info: Detected ripple clock \"data_scanC:inst\|tmp\[8\]\" as buffer" {  } { { "data_scanC.v" "" { Text "D:/Verilog_PS2_1c12/data_scanC.v" 27 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "data_scanC:inst\|tmp\[8\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "data_scanC:inst\|data\[3\]~677 " "Info: Detected gated clock \"data_scanC:inst\|data\[3\]~677\" as buffer" {  } { { "data_scanC.v" "" { Text "D:/Verilog_PS2_1c12/data_scanC.v" 14 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "data_scanC:inst\|data\[3\]~677" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "data_scanC:inst\|tmp\[4\] " "Info: Detected ripple clock \"data_scanC:inst\|tmp\[4\]\" as buffer" {  } { { "data_scanC.v" "" { Text "D:/Verilog_PS2_1c12/data_scanC.v" 27 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "data_scanC:inst\|tmp\[4\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "data_scanC:inst\|tmp\[7\] " "Info: Detected ripple clock \"data_scanC:inst\|tmp\[7\]\" as buffer" {  } { { "data_scanC.v" "" { Text "D:/Verilog_PS2_1c12/data_scanC.v" 27 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "data_scanC:inst\|tmp\[7\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "data_scanC:inst\|data\[2\]~675 " "Info: Detected gated clock \"data_scanC:inst\|data\[2\]~675\" as buffer" {  } { { "data_scanC.v" "" { Text "D:/Verilog_PS2_1c12/data_scanC.v" 14 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "data_scanC:inst\|data\[2\]~675" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "data_scanC:inst\|tmp\[3\] " "Info: Detected ripple clock \"data_scanC:inst\|tmp\[3\]\" as buffer" {  } { { "data_scanC.v" "" { Text "D:/Verilog_PS2_1c12/data_scanC.v" 27 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "data_scanC:inst\|tmp\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "convert:inst1\|reduce_or~1301 " "Info: Detected gated clock \"convert:inst1\|reduce_or~1301\" as buffer" {  } { { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "convert:inst1\|reduce_or~1301" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "data_scanC:inst\|data\[7\]~678 " "Info: Detected gated clock \"data_scanC:inst\|data\[7\]~678\" as buffer" {  } { { "data_scanC.v" "" { Text "D:/Verilog_PS2_1c12/data_scanC.v" 14 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "data_scanC:inst\|data\[7\]~678" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "data_scanC:inst\|data\[6\]~676 " "Info: Detected gated clock \"data_scanC:inst\|data\[6\]~676\" as buffer" {  } { { "data_scanC.v" "" { Text "D:/Verilog_PS2_1c12/data_scanC.v" 14 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "data_scanC:inst\|data\[6\]~676" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "data_scanC:inst\|data\[5\]~674 " "Info: Detected gated clock \"data_scanC:inst\|data\[5\]~674\" as buffer" {  } { { "data_scanC.v" "" { Text "D:/Verilog_PS2_1c12/data_scanC.v" 14 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "data_scanC:inst\|data\[5\]~674" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "data_scanC:inst\|tmp\[6\] " "Info: Detected ripple clock \"data_scanC:inst\|tmp\[6\]\" as buffer" {  } { { "data_scanC.v" "" { Text "D:/Verilog_PS2_1c12/data_scanC.v" 27 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "data_scanC:inst\|tmp\[6\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "data_scanC:inst\|data\[1\]~673 " "Info: Detected gated clock \"data_scanC:inst\|data\[1\]~673\" as buffer" {  } { { "data_scanC.v" "" { Text "D:/Verilog_PS2_1c12/data_scanC.v" 14 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "data_scanC:inst\|data\[1\]~673" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "data_scanC:inst\|tmp\[2\] " "Info: Detected ripple clock \"data_scanC:inst\|tmp\[2\]\" as buffer" {  } { { "data_scanC.v" "" { Text "D:/Verilog_PS2_1c12/data_scanC.v" 27 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "data_scanC:inst\|tmp\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "data_scanC:inst\|ZHJS~reg0 " "Info: Detected ripple clock \"data_scanC:inst\|ZHJS~reg0\" as buffer" {  } { { "data_scanC.v" "" { Text "D:/Verilog_PS2_1c12/data_scanC.v" 27 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "data_scanC:inst\|ZHJS~reg0" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "data_scanC:inst\|data\[4\]~672 " "Info: Detected gated clock \"data_scanC:inst\|data\[4\]~672\" as buffer" {  } { { "data_scanC.v" "" { Text "D:/Verilog_PS2_1c12/data_scanC.v" 14 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "data_scanC:inst\|data\[4\]~672" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "data_scanC:inst\|tmp\[5\] " "Info: Detected ripple clock \"data_scanC:inst\|tmp\[5\]\" as buffer" {  } { { "data_scanC.v" "" { Text "D:/Verilog_PS2_1c12/data_scanC.v" 27 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "data_scanC:inst\|tmp\[5\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "data_scanC:inst\|data\[0\]~671 " "Info: Detected gated clock \"data_scanC:inst\|data\[0\]~671\" as buffer" {  } { { "data_scanC.v" "" { Text "D:/Verilog_PS2_1c12/data_scanC.v" 14 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "data_scanC:inst\|data\[0\]~671" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "data_scanC:inst\|started " "Info: Detected ripple clock \"data_scanC:inst\|started\" as buffer" {  } { { "data_scanC.v" "" { Text "D:/Verilog_PS2_1c12/data_scanC.v" 21 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "data_scanC:inst\|started" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lpm_counter0:inst5\|lpm_counter:lpm_counter_component\|cntr_69d:auto_generated\|safe_q\[0\] " "Info: Detected ripple clock \"lpm_counter0:inst5\|lpm_counter:lpm_counter_component\|cntr_69d:auto_generated\|safe_q\[0\]\" as buffer" {  } { { "db/cntr_69d.tdf" "" { Text "D:/Verilog_PS2_1c12/db/cntr_69d.tdf" 98 8 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lpm_counter0:inst5\|lpm_counter:lpm_counter_component\|cntr_69d:auto_generated\|safe_q\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "data_scanC:inst\|tmp\[1\] " "Info: Detected ripple clock \"data_scanC:inst\|tmp\[1\]\" as buffer" {  } { { "data_scanC.v" "" { Text "D:/Verilog_PS2_1c12/data_scanC.v" 27 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "data_scanC:inst\|tmp\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lpm_counter0:inst5\|lpm_counter:lpm_counter_component\|cntr_69d:auto_generated\|safe_q\[5\] " "Info: Detected ripple clock \"lpm_counter0:inst5\|lpm_counter:lpm_counter_component\|cntr_69d:auto_generated\|safe_q\[5\]\" as buffer" {  } { { "db/cntr_69d.tdf" "" { Text "D:/Verilog_PS2_1c12/db/cntr_69d.tdf" 98 8 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lpm_counter0:inst5\|lpm_counter:lpm_counter_component\|cntr_69d:auto_generated\|safe_q\[5\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register convert:inst1\|mydff:dff_component2\|lpm_ff:lpm_ff_component\|dffs\[0\] register convert:inst1\|tmpASCII\[0\] 50.21 MHz 19.916 ns Internal " "Info: Clock \"clk\" has Internal fmax of 50.21 MHz between source register \"convert:inst1\|mydff:dff_component2\|lpm_ff:lpm_ff_component\|dffs\[0\]\" and destination register \"convert:inst1\|tmpASCII\[0\]\" (period= 19.916 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.321 ns + Longest register register " "Info: + Longest register to register delay is 10.321 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns convert:inst1\|mydff:dff_component2\|lpm_ff:lpm_ff_component\|dffs\[0\] 1 REG LC_X10_Y8_N6 26 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y8_N6; Fanout = 26; REG Node = 'convert:inst1\|mydff:dff_component2\|lpm_ff:lpm_ff_component\|dffs\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "PS2" "UNKNOWN" "V1" "D:/Verilog_PS2_1c12/db/PS2.quartus_db" { Floorplan "D:/Verilog_PS2_1c12/" "" "" { convert:inst1|mydff:dff_component2|lpm_ff:lpm_ff_component|dffs[0] } "NODE_NAME" } "" } } { "lpm_ff.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/lpm_ff.tdf" 60 7 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.087 ns) + CELL(0.200 ns) 2.287 ns convert:inst1\|Select~12175 2 COMB LC_X9_Y7_N9 1 " "Info: 2: + IC(2.087 ns) + CELL(0.200 ns) = 2.287 ns; Loc. = LC_X9_Y7_N9; Fanout = 1; COMB Node = 'convert:inst1\|Select~12175'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "PS2" "UNKNOWN" "V1" "D:/Verilog_PS2_1c12/db/PS2.quartus_db" { Floorplan "D:/Verilog_PS2_1c12/" "" "2.287 ns" { convert:inst1|mydff:dff_component2|lpm_ff:lpm_ff_component|dffs[0] convert:inst1|Select~12175 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.714 ns) + CELL(0.200 ns) 3.201 ns convert:inst1\|Select~12176 3 COMB LC_X9_Y7_N0 1 " "Info: 3: + IC(0.714 ns) + CELL(0.200 ns) = 3.201 ns; Loc. = LC_X9_Y7_N0; Fanout = 1; COMB Node = 'convert:inst1\|Select~12176'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "PS2" "UNKNOWN" "V1" "D:/Verilog_PS2_1c12/db/PS2.quartus_db" { Floorplan "D:/Verilog_PS2_1c12/" "" "0.914 ns" { convert:inst1|Select~12175 convert:inst1|Select~12176 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.923 ns) + CELL(0.200 ns) 5.324 ns convert:inst1\|Select~12049 4 COMB LC_X10_Y8_N0 1 " "Info: 4: + IC(1.923 ns) + CELL(0.200 ns) = 5.324 ns; Loc. = LC_X10_Y8_N0; Fanout = 1; COMB Node = 'convert:inst1\|Select~12049'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "PS2" "UNKNOWN" "V1" "D:/Verilog_PS2_1c12/db/PS2.quartus_db" { Floorplan "D:/Verilog_PS2_1c12/" "" "2.123 ns" { convert:inst1|Select~12176 convert:inst1|Select~12049 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 5.829 ns convert:inst1\|Select~12050 5 COMB LC_X10_Y8_N1 1 " "Info: 5: + IC(0.305 ns) + CELL(0.200 ns) = 5.829 ns; Loc. = LC_X10_Y8_N1; Fanout = 1; COMB Node = 'convert:inst1\|Select~12050'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "PS2" "UNKNOWN" "V1" "D:/Verilog_PS2_1c12/db/PS2.quartus_db" { Floorplan "D:/Verilog_PS2_1c12/" "" "0.505 ns" { convert:inst1|Select~12049 convert:inst1|Select~12050 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.995 ns) + CELL(0.200 ns) 8.024 ns convert:inst1\|Select~12059 6 COMB LC_X11_Y6_N0 1 " "Info: 6: + IC(1.995 ns) + CELL(0.200 ns) = 8.024 ns; Loc. = LC_X11_Y6_N0; Fanout = 1; COMB Node = 'convert:inst1\|Select~12059'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "PS2" "UNKNOWN" "V1" "D:/Verilog_PS2_1c12/db/PS2.quartus_db" { Floorplan "D:/Verilog_PS2_1c12/" "" "2.195 ns" { convert:inst1|Select~12050 convert:inst1|Select~12059 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.097 ns) + CELL(0.200 ns) 10.321 ns convert:inst1\|tmpASCII\[0\] 7 REG LC_X12_Y10_N3 2 " "Info: 7: + IC(2.097 ns) + CELL(0.200 ns) = 10.321 ns; Loc. = LC_X12_Y10_N3; Fanout = 2; REG Node = 'convert:inst1\|tmpASCII\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "PS2" "UNKNOWN" "V1" "D:/Verilog_PS2_1c12/db/PS2.quartus_db" { Floorplan "D:/Verilog_PS2_1c12/" "" "2.297 ns" { convert:inst1|Select~12059 convert:inst1|tmpASCII[0] } "NODE_NAME" } "" } } { "convert.v" "" { Text "D:/Verilog_PS2_1c12/convert.v" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.200 ns ( 11.63 % ) " "Info: Total cell delay = 1.200 ns ( 11.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.121 ns ( 88.37 % ) " "Info: Total interconnect delay = 9.121 ns ( 88.37 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "PS2" "UNKNOWN" "V1" "D:/Verilog_PS2_1c12/db/PS2.quartus_db" { Floorplan "D:/Verilog_PS2_1c12/" "" "10.321 ns" { convert:inst1|mydff:dff_component2|lpm_ff:lpm_ff_component|dffs[0] convert:inst1|Select~12175 convert:inst1|Select~12176 convert:inst1|Select~12049 convert:inst1|Select~12050 convert:inst1|Select~12059 convert:inst1|tmpASCII[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "10.321 ns" { convert:inst1|mydff:dff_component2|lpm_ff:lpm_ff_component|dffs[0] convert:inst1|Select~12175 convert:inst1|Select~12176 convert:inst1|Select~12049 convert:inst1|Select~12050 convert:inst1|Select~12059 convert:inst1|tmpASCII[0] } { 0.000ns 2.087ns 0.714ns 1.923ns 0.305ns 1.995ns 2.097ns } { 0.000ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "3.926 ns - Smallest " "Info: - Smallest clock skew is 3.926 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 18.645 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 18.645 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 6 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 6; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "PS2" "UNKNOWN" "V1" "D:/Verilog_PS2_1c12/db/PS2.quartus_db" { Floorplan "D:/Verilog_PS2_1c12/" "" "" { clk } "NODE_NAME" } "" } } { "PS2.bdf" "" { Schematic "D:/Verilog_PS2_1c12/PS2.bdf" { { 360 -128 40 376 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns lpm_counter0:inst5\|lpm_counter:lpm_counter_component\|cntr_69d:auto_generated\|safe_q\[0\] 2 REG LC_X10_Y5_N1 19 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X10_Y5_N1; Fanout = 19; REG Node = 'lpm_counter0:inst5\|lpm_counter:lpm_counter_component\|cntr_69d:auto_generated\|safe_q\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "PS2" "UNKNOWN" "V1" "D:/Verilog_PS2_1c12/db/PS2.quartus_db" { Floorplan "D:/Verilog_PS2_1c12/" "" "3.032 ns" { clk lpm_counter0:inst5|lpm_counter:lpm_counter_component|cntr_69d:auto_generated|safe_q[0] } "NODE_NAME" } "" } } { "db/cntr_69d.tdf" "" { Text "D:/Verilog_PS2_1c12/db/cntr_69d.tdf" 98 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.482 ns) + CELL(1.294 ns) 9.971 ns data_scanC:inst\|started 3 REG LC_X12_Y7_N2 59 " "Info: 3: + IC(4.482 ns) + CELL(1.294 ns) = 9.971 ns; Loc. = LC_X12_Y7_N2; Fanout = 59; REG Node = 'data_scanC:inst\|started'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "PS2" "UNKNOWN" "V1" "D:/Verilog_PS2_1c12/db/PS2.quartus_db" { Floorplan "D:/Verilog_PS2_1c12/" "" "5.776 ns" { lpm_counter0:inst5|lpm_counter:lpm_counter_component|cntr_69d:auto_generated|safe_q[0] data_scanC:inst|started } "NODE_NAME" } "" } } { "data_scanC.v" "" { Text "D:/Verilog_PS2_1c12/data_scanC.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.489 ns) + CELL(0.511 ns) 11.971 ns convert:inst1\|Select~12060 4 COMB LC_X11_Y7_N6 3 " "Info: 4: + IC(1.489 ns) + CELL(0.511 ns) = 11.971 ns; Loc. = LC_X11_Y7_N6; Fanout = 3; COMB Node = 'convert:inst1\|Select~12060'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "PS2" "UNKNOWN" "V1" "D:/Verilog_PS2_1c12/db/PS2.quartus_db" { Floorplan "D:/Verilog_PS2_1c12/" "" "2.000 ns" { data_scanC:inst|started convert:inst1|Select~12060 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 12.476 ns convert:inst1\|reduce_or~1301 5 COMB LC_X11_Y7_N7 1 " "Info: 5: + IC(0.305 ns) + CELL(0.200 ns) = 12.476 ns; Loc. = LC_X11_Y7_N7; Fanout = 1; COMB Node = 'convert:inst1\|reduce_or~1301'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "PS2" "UNKNOWN" "V1" "D:/Verilog_PS2_1c12/db/PS2.quartus_db" { Floorplan "D:/Verilog_PS2_1c12/" "" "0.505 ns" { convert:inst1|Select~12060 convert:inst1|reduce_or~1301 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 12.981 ns convert:inst1\|reduce_or~1308 6 COMB LC_X11_Y7_N8 7 " "Info: 6: + IC(0.305 ns) + CELL(0.200 ns) = 12.981 ns; Loc. = LC_X11_Y7_N8; Fanout = 7; COMB Node = 'convert:inst1\|reduce_or~1308'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "PS2" "UNKNOWN" "V1" "D:/Verilog_PS2_1c12/db/PS2.quartus_db" { Floorplan "D:/Verilog_PS2_1c12/" "" "0.505 ns" { convert:inst1|reduce_or~1301 convert:inst1|reduce_or~1308 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.924 ns) + CELL(0.740 ns) 18.645 ns convert:inst1\|tmpASCII\[0\] 7 REG LC_X12_Y10_N3 2 " "Info: 7: + IC(4.924 ns) + CELL(0.740 ns) = 18.645 ns; Loc. = LC_X12_Y10_N3; Fanout = 2; REG Node = 'convert:inst1\|tmpASCII\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "PS2" "UNKNOWN" "V1" "D:/Verilog_PS2_1c12/db/PS2.quartus_db" { Floorplan "D:/Verilog_PS2_1c12/" "" "5.664 ns" { convert:inst1|reduce_or~1308 convert:inst1|tmpASCII[0] } "NODE_NAME" } "" } } { "convert.v" "" { Text "D:/Verilog_PS2_1c12/convert.v" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.402 ns ( 28.97 % ) " "Info: Total cell delay = 5.402 ns ( 28.97 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "13.243 ns ( 71.03 % ) " "Info: Total interconnect delay = 13.243 ns ( 71.03 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "PS2" "UNKNOWN" "V1" "D:/Verilog_PS2_1c12/db/PS2.quartus_db" { Floorplan "D:/Verilog_PS2_1c12/" "" "18.645 ns" { clk lpm_counter0:inst5|lpm_counter:lpm_counter_component|cntr_69d:auto_generated|safe_q[0] data_scanC:inst|started convert:inst1|Select~12060 convert:inst1|reduce_or~1301 convert:inst1|reduce_or~1308 convert:inst1|tmpASCII[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "18.645 ns" { clk clk~combout lpm_counter0:inst5|lpm_counter:lpm_counter_component|cntr_69d:auto_generated|safe_q[0] data_scanC:inst|started convert:inst1|Select~12060 convert:inst1|reduce_or~1301 convert:inst1|reduce_or~1308 convert:inst1|tmpASCII[0] } { 0.000ns 0.000ns 1.738ns 4.482ns 1.489ns 0.305ns 0.305ns 4.924ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.511ns 0.200ns 0.200ns 0.740ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 14.719 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 14.719 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 6 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 6; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "PS2" "UNKNOWN" "V1" "D:/Verilog_PS2_1c12/db/PS2.quartus_db" { Floorplan "D:/Verilog_PS2_1c12/" "" "" { clk } "NODE_NAME" } "" } } { "PS2.bdf" "" { Schematic "D:/Verilog_PS2_1c12/PS2.bdf" { { 360 -128 40 376 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns lpm_counter0:inst5\|lpm_counter:lpm_counter_component\|cntr_69d:auto_generated\|safe_q\[0\] 2 REG LC_X10_Y5_N1 19 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X10_Y5_N1; Fanout = 19; REG Node = 'lpm_counter0:inst5\|lpm_counter:lpm_counter_component\|cntr_69d:auto_generated\|safe_q\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "PS2" "UNKNOWN" "V1" "D:/Verilog_PS2_1c12/db/PS2.quartus_db" { Floorplan "D:/Verilog_PS2_1c12/" "" "3.032 ns" { clk lpm_counter0:inst5|lpm_counter:lpm_counter_component|cntr_69d:auto_generated|safe_q[0] } "NODE_NAME" } "" } } { "db/cntr_69d.tdf" "" { Text "D:/Verilog_PS2_1c12/db/cntr_69d.tdf" 98 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.482 ns) + CELL(1.294 ns) 9.971 ns data_scanC:inst\|ZHJS~reg0 3 REG LC_X12_Y5_N9 3 " "Info: 3: + IC(4.482 ns) + CELL(1.294 ns) = 9.971 ns; Loc. = LC_X12_Y5_N9; Fanout = 3; REG Node = 'data_scanC:inst\|ZHJS~reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "PS2" "UNKNOWN" "V1" "D:/Verilog_PS2_1c12/db/PS2.quartus_db" { Floorplan "D:/Verilog_PS2_1c12/" "" "5.776 ns" { lpm_counter0:inst5|lpm_counter:lpm_counter_component|cntr_69d:auto_generated|safe_q[0] data_scanC:inst|ZHJS~reg0 } "NODE_NAME" } "" } } { "data_scanC.v" "" { Text "D:/Verilog_PS2_1c12/data_scanC.v" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.830 ns) + CELL(0.918 ns) 14.719 ns convert:inst1\|mydff:dff_component2\|lpm_ff:lpm_ff_component\|dffs\[0\] 4 REG LC_X10_Y8_N6 26 " "Info: 4: + IC(3.830 ns) + CELL(0.918 ns) = 14.719 ns; Loc. = LC_X10_Y8_N6; Fanout = 26; REG Node = 'convert:inst1\|mydff:dff_component2\|lpm_ff:lpm_ff_component\|dffs\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "PS2" "UNKNOWN" "V1" "D:/Verilog_PS2_1c12/db/PS2.quartus_db" { Floorplan "D:/Verilog_PS2_1c12/" "" "4.748 ns" { data_scanC:inst|ZHJS~reg0 convert:inst1|mydff:dff_component2|lpm_ff:lpm_ff_component|dffs[0] } "NODE_NAME" } "" } } { "lpm_ff.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/lpm_ff.tdf" 60 7 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.669 ns ( 31.72 % ) " "Info: Total cell delay = 4.669 ns ( 31.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.050 ns ( 68.28 % ) " "Info: Total interconnect delay = 10.050 ns ( 68.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "PS2" "UNKNOWN" "V1" "D:/Verilog_PS2_1c12/db/PS2.quartus_db" { Floorplan "D:/Verilog_PS2_1c12/" "" "14.719 ns" { clk lpm_counter0:inst5|lpm_counter:lpm_counter_component|cntr_69d:auto_generated|safe_q[0] data_scanC:inst|ZHJS~reg0 convert:inst1|mydff:dff_component2|lpm_ff:lpm_ff_component|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "14.719 ns" { clk clk~combout lpm_counter0:inst5|lpm_counter:lpm_counter_component|cntr_69d:auto_generated|safe_q[0] data_scanC:inst|ZHJS~reg0 convert:inst1|mydff:dff_component2|lpm_ff:lpm_ff_component|dffs[0] } { 0.000ns 0.000ns 1.738ns 4.482ns 3.830ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "PS2" "UNKNOWN" "V1" "D:/Verilog_PS2_1c12/db/PS2.quartus_db" { Floorplan "D:/Verilog_PS2_1c12/" "" "18.645 ns" { clk lpm_counter0:inst5|lpm_counter:lpm_counter_component|cntr_69d:auto_generated|safe_q[0] data_scanC:inst|started convert:inst1|Select~12060 convert:inst1|reduce_or~1301 convert:inst1|reduce_or~1308 convert:inst1|tmpASCII[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "18.645 ns" { clk clk~combout lpm_counter0:inst5|lpm_counter:lpm_counter_component|cntr_69d:auto_generated|safe_q[0] data_scanC:inst|started convert:inst1|Select~12060 convert:inst1|reduce_or~1301 convert:inst1|reduce_or~1308 convert:inst1|tmpASCII[0] } { 0.000ns 0.000ns 1.738ns 4.482ns 1.489ns 0.305ns 0.305ns 4.924ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.511ns 0.200ns 0.200ns 0.740ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "PS2" "UNKNOWN" "V1" "D:/Verilog_PS2_1c12/db/PS2.quartus_db" { Floorplan "D:/Verilog_PS2_1c12/" "" "14.719 ns" { clk lpm_counter0:inst5|lpm_counter:lpm_counter_component|cntr_69d:auto_generated|safe_q[0] data_scanC:inst|ZHJS~reg0 convert:inst1|mydff:dff_component2|lpm_ff:lpm_ff_component|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "14.719 ns" { clk clk~combout lpm_counter0:inst5|lpm_counter:lpm_counter_component|cntr_69d:auto_generated|safe_q[0] data_scanC:inst|ZHJS~reg0 convert:inst1|mydff:dff_component2|lpm_ff:lpm_ff_component|dffs[0] } { 0.000ns 0.000ns 1.738ns 4.482ns 3.830ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "lpm_ff.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/lpm_ff.tdf" 60 7 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "3.187 ns + " "Info: + Micro setup delay of destination is 3.187 ns" {  } { { "convert.v" "" { Text "D:/Verilog_PS2_1c12/convert.v" 59 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "lpm_ff.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/lpm_ff.tdf" 60 7 0 } } { "convert.v" "" { Text "D:/Verilog_PS2_1c12/convert.v" 59 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "PS2" "UNKNOWN" "V1" "D:/Verilog_PS2_1c12/db/PS2.quartus_db" { Floorplan "D:/Verilog_PS2_1c12/" "" "10.321 ns" { convert:inst1|mydff:dff_component2|lpm_ff:lpm_ff_component|dffs[0] convert:inst1|Select~12175 convert:inst1|Select~12176 convert:inst1|Select~12049 convert:inst1|Select~12050 convert:inst1|Select~12059 convert:inst1|tmpASCII[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "10.321 ns" { convert:inst1|mydff:dff_component2|lpm_ff:lpm_ff_component|dffs[0] convert:inst1|Select~12175 convert:inst1|Select~12176 convert:inst1|Select~12049 convert:inst1|Select~12050 convert:inst1|Select~12059 convert:inst1|tmpASCII[0] } { 0.000ns 2.087ns 0.714ns 1.923ns 0.305ns 1.995ns 2.097ns } { 0.000ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "PS2" "UNKNOWN" "V1" "D:/Verilog_PS2_1c12/db/PS2.quartus_db" { Floorplan "D:/Verilog_PS2_1c12/" "" "18.645 ns" { clk lpm_counter0:inst5|lpm_counter:lpm_counter_component|cntr_69d:auto_generated|safe_q[0] data_scanC:inst|started convert:inst1|Select~12060 convert:inst1|reduce_or~1301 convert:inst1|reduce_or~1308 convert:inst1|tmpASCII[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "18.645 ns" { clk clk~combout lpm_counter0:inst5|lpm_counter:lpm_counter_component|cntr_69d:auto_generated|safe_q[0] data_scanC:inst|started convert:inst1|Select~12060 convert:inst1|reduce_or~1301 convert:inst1|reduce_or~1308 convert:inst1|tmpASCII[0] } { 0.000ns 0.000ns 1.738ns 4.482ns 1.489ns 0.305ns 0.305ns 4.924ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.511ns 0.200ns 0.200ns 0.740ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "PS2" "UNKNOWN" "V1" "D:/Verilog_PS2_1c12/db/PS2.quartus_db" { Floorplan "D:/Verilog_PS2_1c12/" "" "14.719 ns" { clk lpm_counter0:inst5|lpm_counter:lpm_counter_component|cntr_69d:auto_generated|safe_q[0] data_scanC:inst|ZHJS~reg0 convert:inst1|mydff:dff_component2|lpm_ff:lpm_ff_component|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "14.719 ns" { clk clk~combout lpm_counter0:inst5|lpm_counter:lpm_counter_component|cntr_69d:auto_generated|safe_q[0] data_scanC:inst|ZHJS~reg0 convert:inst1|mydff:dff_component2|lpm_ff:lpm_ff_component|dffs[0] } { 0.000ns 0.000ns 1.738ns 4.482ns 3.830ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}