ps2.tan.qmsg

Verilog 经典实例

{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Warning" "WTAN_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTAN_COMB_LATCH_NODE" "convert:inst1\|tmpASCII\[4\] " "Warning: Node \"convert:inst1\|tmpASCII\[4\]\" is a latch" {  } { { "convert.v" "" { Text "D:/Verilog_PS2_1c12/convert.v" 59 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "convert:inst1\|tmpASCII\[0\] " "Warning: Node \"convert:inst1\|tmpASCII\[0\]\" is a latch" {  } { { "convert.v" "" { Text "D:/Verilog_PS2_1c12/convert.v" 59 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "convert:inst1\|tmpASCII\[6\] " "Warning: Node \"convert:inst1\|tmpASCII\[6\]\" is a latch" {  } { { "convert.v" "" { Text "D:/Verilog_PS2_1c12/convert.v" 59 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "convert:inst1\|tmpASCII\[1\] " "Warning: Node \"convert:inst1\|tmpASCII\[1\]\" is a latch" {  } { { "convert.v" "" { Text "D:/Verilog_PS2_1c12/convert.v" 59 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "convert:inst1\|tmpASCII\[2\] " "Warning: Node \"convert:inst1\|tmpASCII\[2\]\" is a latch" {  } { { "convert.v" "" { Text "D:/Verilog_PS2_1c12/convert.v" 59 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "convert:inst1\|tmpASCII\[3\] " "Warning: Node \"convert:inst1\|tmpASCII\[3\]\" is a latch" {  } { { "convert.v" "" { Text "D:/Verilog_PS2_1c12/convert.v" 59 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "convert:inst1\|tmpASCII\[5\] " "Warning: Node \"convert:inst1\|tmpASCII\[5\]\" is a latch" {  } { { "convert.v" "" { Text "D:/Verilog_PS2_1c12/convert.v" 59 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0}