ps2.fit.qmsg

Verilog 经典实例

{ "Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Info: Moving registers into LUTs to improve timing and density" {  } {  } 0 0 "Moving registers into LUTs to improve timing and density" 0 0}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Info: Started processing fast register assignments" {  } {  } 0 0 "Started processing fast register assignments" 0 0}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Info: Finished processing fast register assignments" {  } {  } 0 0 "Finished processing fast register assignments" 0 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "" "Info: Finished moving registers into LUTs" {  } {  } 0 0 "Finished moving registers into LUTs" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0 0 "Finished register packing" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:07 " "Info: Fitter placement operations ending: elapsed time is 00:00:07" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "12.917 ns register pin " "Info: Estimated most critical path is register to pin delay of 12.917 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns convert:inst1\|tmpASCII\[6\] 1 REG LAB_X12_Y10 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X12_Y10; Fanout = 1; REG Node = 'convert:inst1\|tmpASCII\[6\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "PS2" "UNKNOWN" "V1" "D:/Verilog_PS2_1c12/db/PS2.quartus_db" { Floorplan "D:/Verilog_PS2_1c12/" "" "" { convert:inst1|tmpASCII[6] } "NODE_NAME" } "" } } { "convert.v" "" { Text "D:/Verilog_PS2_1c12/convert.v" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.345 ns) + CELL(0.914 ns) 1.259 ns segmain:inst9\|dataout\[2\]~569 2 COMB LAB_X12_Y10 2 " "Info: 2: + IC(0.345 ns) + CELL(0.914 ns) = 1.259 ns; Loc. = LAB_X12_Y10; Fanout = 2; COMB Node = 'segmain:inst9\|dataout\[2\]~569'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "PS2" "UNKNOWN" "V1" "D:/Verilog_PS2_1c12/db/PS2.quartus_db" { Floorplan "D:/Verilog_PS2_1c12/" "" "1.259 ns" { convert:inst1|tmpASCII[6] segmain:inst9|dataout[2]~569 } "NODE_NAME" } "" } } { "segmain.v" "" { Text "D:/Verilog_PS2_1c12/segmain.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.269 ns) + CELL(0.914 ns) 2.442 ns segmain:inst9\|dataout\[1\]~570 3 COMB LAB_X12_Y10 1 " "Info: 3: + IC(0.269 ns) + CELL(0.914 ns) = 2.442 ns; Loc. = LAB_X12_Y10; Fanout = 1; COMB Node = 'segmain:inst9\|dataout\[1\]~570'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "PS2" "UNKNOWN" "V1" "D:/Verilog_PS2_1c12/db/PS2.quartus_db" { Floorplan "D:/Verilog_PS2_1c12/" "" "1.183 ns" { segmain:inst9|dataout[2]~569 segmain:inst9|dataout[1]~570 } "NODE_NAME" } "" } } { "segmain.v" "" { Text "D:/Verilog_PS2_1c12/segmain.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.443 ns) + CELL(0.740 ns) 3.625 ns segmain:inst9\|dataout\[1\]~572 4 COMB LAB_X12_Y10 1 " "Info: 4: + IC(0.443 ns) + CELL(0.740 ns) = 3.625 ns; Loc. = LAB_X12_Y10; Fanout = 1; COMB Node = 'segmain:inst9\|dataout\[1\]~572'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "PS2" "UNKNOWN" "V1" "D:/Verilog_PS2_1c12/db/PS2.quartus_db" { Floorplan "D:/Verilog_PS2_1c12/" "" "1.183 ns" { segmain:inst9|dataout[1]~570 segmain:inst9|dataout[1]~572 } "NODE_NAME" } "" } } { "segmain.v" "" { Text "D:/Verilog_PS2_1c12/segmain.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.749 ns) + CELL(0.914 ns) 5.288 ns segmain:inst9\|dataout\[1\]~573 5 COMB LAB_X11_Y10 1 " "Info: 5: + IC(0.749 ns) + CELL(0.914 ns) = 5.288 ns; Loc. = LAB_X11_Y10; Fanout = 1; COMB Node = 'segmain:inst9\|dataout\[1\]~573'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "PS2" "UNKNOWN" "V1" "D:/Verilog_PS2_1c12/db/PS2.quartus_db" { Floorplan "D:/Verilog_PS2_1c12/" "" "1.663 ns" { segmain:inst9|dataout[1]~572 segmain:inst9|dataout[1]~573 } "NODE_NAME" } "" } } { "segmain.v" "" { Text "D:/Verilog_PS2_1c12/segmain.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.443 ns) + CELL(0.740 ns) 6.471 ns segmain:inst9\|dataout\[1\]~574 6 COMB LAB_X11_Y10 1 " "Info: 6: + IC(0.443 ns) + CELL(0.740 ns) = 6.471 ns; Loc. = LAB_X11_Y10; Fanout = 1; COMB Node = 'segmain:inst9\|dataout\[1\]~574'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "PS2" "UNKNOWN" "V1" "D:/Verilog_PS2_1c12/db/PS2.quartus_db" { Floorplan "D:/Verilog_PS2_1c12/" "" "1.183 ns" { segmain:inst9|dataout[1]~573 segmain:inst9|dataout[1]~574 } "NODE_NAME" } "" } } { "segmain.v" "" { Text "D:/Verilog_PS2_1c12/segmain.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.983 ns) + CELL(0.200 ns) 7.654 ns segmain:inst9\|dataout\[1\] 7 COMB LAB_X11_Y10 7 " "Info: 7: + IC(0.983 ns) + CELL(0.200 ns) = 7.654 ns; Loc. = LAB_X11_Y10; Fanout = 7; COMB Node = 'segmain:inst9\|dataout\[1\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "PS2" "UNKNOWN" "V1" "D:/Verilog_PS2_1c12/db/PS2.quartus_db" { Floorplan "D:/Verilog_PS2_1c12/" "" "1.183 ns" { segmain:inst9|dataout[1]~574 segmain:inst9|dataout[1] } "NODE_NAME" } "" } } { "segmain.v" "" { Text "D:/Verilog_PS2_1c12/segmain.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.626 ns) + CELL(0.740 ns) 10.020 ns bin27seg:inst3\|data_out\[4\]~74 8 COMB LAB_X13_Y10 1 " "Info: 8: + IC(1.626 ns) + CELL(0.740 ns) = 10.020 ns; Loc. = LAB_X13_Y10; Fanout = 1; COMB Node = 'bin27seg:inst3\|data_out\[4\]~74'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "PS2" "UNKNOWN" "V1" "D:/Verilog_PS2_1c12/db/PS2.quartus_db" { Floorplan "D:/Verilog_PS2_1c12/" "" "2.366 ns" { segmain:inst9|dataout[1] bin27seg:inst3|data_out[4]~74 } "NODE_NAME" } "" } } { "bin27seg.v" "" { Text "D:/Verilog_PS2_1c12/bin27seg.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.575 ns) + CELL(2.322 ns) 12.917 ns seg7\[4\] 9 PIN PIN_113 0 " "Info: 9: + IC(0.575 ns) + CELL(2.322 ns) = 12.917 ns; Loc. = PIN_113; Fanout = 0; PIN Node = 'seg7\[4\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "PS2" "UNKNOWN" "V1" "D:/Verilog_PS2_1c12/db/PS2.quartus_db" { Floorplan "D:/Verilog_PS2_1c12/" "" "2.897 ns" { bin27seg:inst3|data_out[4]~74 seg7[4] } "NODE_NAME" } "" } } { "PS2.bdf" "" { Schematic "D:/Verilog_PS2_1c12/PS2.bdf" { { 216 424 600 232 "seg7\[6..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.484 ns ( 57.94 % ) " "Info: Total cell delay = 7.484 ns ( 57.94 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.433 ns ( 42.06 % ) " "Info: Total interconnect delay = 5.433 ns ( 42.06 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "PS2" "UNKNOWN" "V1" "D:/Verilog_PS2_1c12/db/PS2.quartus_db" { Floorplan "D:/Verilog_PS2_1c12/" "" "12.917 ns" { convert:inst1|tmpASCII[6] segmain:inst9|dataout[2]~569 segmain:inst9|dataout[1]~570 segmain:inst9|dataout[1]~572 segmain:inst9|dataout[1]~573 segmain:inst9|dataout[1]~574 segmain:inst9|dataout[1] bin27seg:inst3|data_out[4]~74 seg7[4] } "NODE_NAME" } "" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "4 7 " "Info: Average interconnect usage is 4% of the available device resources. Peak interconnect usage is 7%" {  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:09 " "Info: Fitter routing operations ending: elapsed time is 00:00:09" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_NOT_USED" "" "Info: The Fitter performed an Auto Fit compilation.  No optimizations were skipped because the design's timing and routability requirements required full optimization." {  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  No optimizations were skipped because the design's timing and routability requirements required full optimization." 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Nov 19 23:03:12 2006 " "Info: Processing ended: Sun Nov 19 23:03:12 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:24 " "Info: Elapsed time: 00:00:24" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}