dianzhen.vhd

来自「用vhdl做得CPLD静态两位数码管扫描 显示“10”两位数码管公用段选」· VHDL 代码 · 共 37 行

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
USE IEEE.Std_Logic_Unsigned.ALL;

ENTITY dianzhen IS
 PORT(
		INK01,INK02,INK03,INK04,INK05,INK06,INK07,INK08,INV01,INV02,INV03,INV04,INV05,INV06,INV07,INV08	        : OUT	STD_LOGIC
 );
END dianzhen;

ARCHITECTURE Count OF dianzhen IS
    SIGNAL INDATA:STD_LOGIC_VECTOR(7 DOWNTO 0);
    SIGNAL TEMP : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
    INV01 <= INDATA(0);
    INV02 <= INDATA(1);
    INV03 <= INDATA(2);
    INV04 <= INDATA(3);
    INV05 <= INDATA(4);
    INV06 <= INDATA(5);
    INV07 <= INDATA(6);
    INV08 <= INDATA(7);
    INK01 <= TEMP(0);
    INK02 <= TEMP(1);
    INK03 <= TEMP(2);
    INK04 <= TEMP(3);
    INK05 <= TEMP(4);
    INK06 <= TEMP(5);
    INK07 <= TEMP(6);
    INK08 <= TEMP(7);
     INDATA<="00000000";
     TEMP<="10100111";
END Count;