dianzhen.rpt

用vhdl做得CPLD静态两位数码管扫描 显示“10”两位数码管公用段选

  44     65    E     OUTPUT      t        0      0   0    0    0    0    0  INV01
  45     67    E     OUTPUT      t        0      0   0    0    0    0    0  INV02
  46     69    E     OUTPUT      t        0      0   0    0    0    0    0  INV03
  48     72    E     OUTPUT      t        0      0   0    0    0    0    0  INV04
  49     73    E     OUTPUT      t        0      0   0    0    0    0    0  INV05
  50     75    E     OUTPUT      t        0      0   0    0    0    0    0  INV06
  51     77    E     OUTPUT      t        0      0   0    0    0    0    0  INV07
  52     80    E     OUTPUT      t        0      0   0    0    0    0    0  INV08


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                       f:\vhdprograme\dianzhen.rpt
dianzhen

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'D':

                         Logic cells placed in LAB 'D'
        +--------------- LC64 INK01
        | +------------- LC61 INK02
        | | +----------- LC59 INK03
        | | | +--------- LC57 INK04
        | | | | +------- LC56 INK05
        | | | | | +----- LC53 INK06
        | | | | | | +--- LC51 INK07
        | | | | | | | +- LC49 INK08
        | | | | | | | | 
        | | | | | | | |   Other LABs fed by signals
        | | | | | | | |   that feed LAB 'D'
LC      | | | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'D':

Pin


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                       f:\vhdprograme\dianzhen.rpt
dianzhen

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'E':

                         Logic cells placed in LAB 'E'
        +--------------- LC65 INV01
        | +------------- LC67 INV02
        | | +----------- LC69 INV03
        | | | +--------- LC72 INV04
        | | | | +------- LC73 INV05
        | | | | | +----- LC75 INV06
        | | | | | | +--- LC77 INV07
        | | | | | | | +- LC80 INV08
        | | | | | | | | 
        | | | | | | | |   Other LABs fed by signals
        | | | | | | | |   that feed LAB 'E'
LC      | | | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'E':

Pin


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                       f:\vhdprograme\dianzhen.rpt
dianzhen

** EQUATIONS **


-- Node name is 'INK01' 
-- Equation name is 'INK01', location is LC064, type is output.
 INK01   = LCELL( GND $  VCC);

-- Node name is 'INK02' 
-- Equation name is 'INK02', location is LC061, type is output.
 INK02   = LCELL( GND $  VCC);

-- Node name is 'INK03' 
-- Equation name is 'INK03', location is LC059, type is output.
 INK03   = LCELL( GND $  VCC);

-- Node name is 'INK04' 
-- Equation name is 'INK04', location is LC057, type is output.
 INK04   = LCELL( GND $  GND);

-- Node name is 'INK05' 
-- Equation name is 'INK05', location is LC056, type is output.
 INK05   = LCELL( GND $  GND);

-- Node name is 'INK06' 
-- Equation name is 'INK06', location is LC053, type is output.
 INK06   = LCELL( GND $  VCC);

-- Node name is 'INK07' 
-- Equation name is 'INK07', location is LC051, type is output.
 INK07   = LCELL( GND $  GND);

-- Node name is 'INK08' 
-- Equation name is 'INK08', location is LC049, type is output.
 INK08   = LCELL( GND $  VCC);

-- Node name is 'INV01' 
-- Equation name is 'INV01', location is LC065, type is output.
 INV01   = LCELL( GND $  GND);

-- Node name is 'INV02' 
-- Equation name is 'INV02', location is LC067, type is output.
 INV02   = LCELL( GND $  GND);

-- Node name is 'INV03' 
-- Equation name is 'INV03', location is LC069, type is output.
 INV03   = LCELL( GND $  GND);

-- Node name is 'INV04' 
-- Equation name is 'INV04', location is LC072, type is output.
 INV04   = LCELL( GND $  GND);

-- Node name is 'INV05' 
-- Equation name is 'INV05', location is LC073, type is output.
 INV05   = LCELL( GND $  GND);

-- Node name is 'INV06' 
-- Equation name is 'INV06', location is LC075, type is output.
 INV06   = LCELL( GND $  GND);

-- Node name is 'INV07' 
-- Equation name is 'INV07', location is LC077, type is output.
 INV07   = LCELL( GND $  GND);

-- Node name is 'INV08' 
-- Equation name is 'INV08', location is LC080, type is output.
 INV08   = LCELL( GND $  GND);



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                f:\vhdprograme\dianzhen.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 3,597K