📄 shuma_2.rpt
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50 75 E OUTPUT t 0 0 0 0 0 0 0 out05
51 77 E OUTPUT t 0 0 0 0 0 0 0 out06
52 80 E OUTPUT t 0 0 0 0 0 0 0 out07
33 64 D OUTPUT t 0 0 0 1 0 0 0 out10
34 61 D OUTPUT t 0 0 0 1 0 0 0 out11
35 59 D OUTPUT t 0 0 0 0 0 0 0 out12
36 57 D OUTPUT t 0 0 0 0 0 0 0 out13
37 56 D OUTPUT t 0 0 0 0 0 0 0 out14
39 53 D OUTPUT t 0 0 0 0 0 0 0 out15
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: f:\vhdprograme\2weishumaguan\shuma_2.rpt
shuma_2
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+----------- LC64 out10
| +--------- LC61 out11
| | +------- LC59 out12
| | | +----- LC57 out13
| | | | +--- LC56 out14
| | | | | +- LC53 out15
| | | | | |
| | | | | | Other LABs fed by signals
| | | | | | that feed LAB 'D'
LC | | | | | | | A B C D E F G H | Logic cells that feed LAB 'D':
Pin
83 -> * * - - - - | - - - * - - - - | <-- data
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: f:\vhdprograme\2weishumaguan\shuma_2.rpt
shuma_2
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'E':
Logic cells placed in LAB 'E'
+--------------- LC65 out00
| +------------- LC67 out01
| | +----------- LC69 out02
| | | +--------- LC72 out03
| | | | +------- LC73 out04
| | | | | +----- LC75 out05
| | | | | | +--- LC77 out06
| | | | | | | +- LC80 out07
| | | | | | | |
| | | | | | | | Other LABs fed by signals
| | | | | | | | that feed LAB 'E'
LC | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'E':
Pin
83 -> - - - - - - - - | - - - * - - - - | <-- data
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: f:\vhdprograme\2weishumaguan\shuma_2.rpt
shuma_2
** EQUATIONS **
data : INPUT;
-- Node name is 'out00'
-- Equation name is 'out00', location is LC065, type is output.
out00 = LCELL( GND $ GND);
-- Node name is 'out01'
-- Equation name is 'out01', location is LC067, type is output.
out01 = LCELL( GND $ VCC);
-- Node name is 'out02'
-- Equation name is 'out02', location is LC069, type is output.
out02 = LCELL( GND $ VCC);
-- Node name is 'out03'
-- Equation name is 'out03', location is LC072, type is output.
out03 = LCELL( GND $ GND);
-- Node name is 'out04'
-- Equation name is 'out04', location is LC073, type is output.
out04 = LCELL( GND $ GND);
-- Node name is 'out05'
-- Equation name is 'out05', location is LC075, type is output.
out05 = LCELL( GND $ GND);
-- Node name is 'out06'
-- Equation name is 'out06', location is LC077, type is output.
out06 = LCELL( GND $ GND);
-- Node name is 'out07'
-- Equation name is 'out07', location is LC080, type is output.
out07 = LCELL( GND $ GND);
-- Node name is 'out10'
-- Equation name is 'out10', location is LC064, type is output.
out10 = LCELL(!data $ GND);
-- Node name is 'out11'
-- Equation name is 'out11', location is LC061, type is output.
out11 = LCELL(!data $ VCC);
-- Node name is 'out12'
-- Equation name is 'out12', location is LC059, type is output.
out12 = LCELL( VCC $ VCC);
-- Node name is 'out13'
-- Equation name is 'out13', location is LC057, type is output.
out13 = LCELL( VCC $ VCC);
-- Node name is 'out14'
-- Equation name is 'out14', location is LC056, type is output.
out14 = LCELL( VCC $ VCC);
-- Node name is 'out15'
-- Equation name is 'out15', location is LC053, type is output.
out15 = LCELL( VCC $ VCC);
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information f:\vhdprograme\2weishumaguan\shuma_2.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = off
Automatic Global Clear = off
Automatic Global Preset = off
Automatic Global Output Enable = off
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:01
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 4,132K
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