📄 maichong.rpt
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Device-Specific Information: f:\vhdprograme\maichong\maichong.rpt
maichong
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
- 98 G DFFE + t 1 0 0 2 4 7 4 cnt03 (:12)
- 100 G TFFE + t 0 0 0 2 4 7 3 cnt02 (:13)
- 102 G DFFE + t 0 0 0 2 3 7 4 cnt01 (:14)
- 103 G DFFE + t 0 0 0 2 4 7 4 cnt00 (:15)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: f:\vhdprograme\maichong\maichong.rpt
maichong
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'F':
Logic cells placed in LAB 'F'
+- LC94 out07
|
| Other LABs fed by signals
| that feed LAB 'F'
LC | | A B C D E F G H | Logic cells that feed LAB 'F':
Pin
83 -> - | - - - - - - - - | <-- data
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: f:\vhdprograme\maichong\maichong.rpt
maichong
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'G':
Logic cells placed in LAB 'G'
+--------------------- LC109 out00
| +------------------- LC107 out01
| | +----------------- LC105 out02
| | | +--------------- LC104 out03
| | | | +------------- LC101 out04
| | | | | +----------- LC99 out05
| | | | | | +--------- LC97 out06
| | | | | | | +------- LC98 cnt03
| | | | | | | | +----- LC100 cnt02
| | | | | | | | | +--- LC102 cnt01
| | | | | | | | | | +- LC103 cnt00
| | | | | | | | | | |
| | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | that feed LAB 'G'
LC | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'G':
LC98 -> * * * * * * * * * * * | - - - - - - * - | <-- cnt03
LC100-> * * * * * * * * * - * | - - - - - - * - | <-- cnt02
LC102-> * * * * * * * * * * * | - - - - - - * - | <-- cnt01
LC103-> * * * * * * * * * * * | - - - - - - * - | <-- cnt00
Pin
83 -> - - - - - - - - - - - | - - - - - - - - | <-- data
15 -> - - - - - - - * * * * | - - - - - - * - | <-- en
16 -> - - - - - - - * * * * | - - - - - - * - | <-- reset
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: f:\vhdprograme\maichong\maichong.rpt
maichong
** EQUATIONS **
data : INPUT;
en : INPUT;
reset : INPUT;
-- Node name is ':15' = 'cnt00'
-- Equation name is 'cnt00', location is LC103, type is buried.
cnt00 = DFFE( _EQ001 $ GND, GLOBAL( data), !reset, VCC, VCC);
_EQ001 = !cnt00 & !cnt01 & !cnt02 & cnt03 & en
# !cnt00 & !cnt03 & en
# cnt00 & !en;
-- Node name is ':14' = 'cnt01'
-- Equation name is 'cnt01', location is LC102, type is buried.
cnt01 = DFFE( _EQ002 $ GND, GLOBAL( data), !reset, VCC, VCC);
_EQ002 = !cnt00 & cnt01 & !cnt03 & en
# cnt00 & !cnt01 & !cnt03 & en
# cnt01 & !en;
-- Node name is ':13' = 'cnt02'
-- Equation name is 'cnt02', location is LC100, type is buried.
cnt02 = TFFE( _EQ003, GLOBAL( data), !reset, VCC, VCC);
_EQ003 = cnt00 & cnt01 & !cnt02 & !cnt03 & en
# cnt00 & cnt01 & cnt02 & en
# cnt02 & cnt03 & en;
-- Node name is ':12' = 'cnt03'
-- Equation name is 'cnt03', location is LC098, type is buried.
cnt03 = DFFE( _EQ004 $ GND, GLOBAL( data), !reset, VCC, VCC);
_EQ004 = !cnt00 & !cnt01 & !cnt02 & cnt03 & en & _X001
# cnt00 & cnt01 & cnt02 & !cnt03 & en
# cnt03 & !en;
_X001 = EXP( cnt00 & cnt01 & cnt02);
-- Node name is 'out00'
-- Equation name is 'out00', location is LC109, type is output.
out00 = LCELL( _EQ005 $ VCC);
_EQ005 = !cnt00 & !cnt01 & cnt02 & !cnt03
# cnt00 & !cnt01 & !cnt02 & !cnt03;
-- Node name is 'out01'
-- Equation name is 'out01', location is LC107, type is output.
out01 = LCELL( _EQ006 $ VCC);
_EQ006 = !cnt00 & cnt01 & cnt02 & !cnt03
# cnt00 & !cnt01 & cnt02 & !cnt03;
-- Node name is 'out02'
-- Equation name is 'out02', location is LC105, type is output.
out02 = LCELL( _EQ007 $ VCC);
_EQ007 = !cnt00 & cnt01 & !cnt02 & !cnt03;
-- Node name is 'out03'
-- Equation name is 'out03', location is LC104, type is output.
out03 = LCELL( _EQ008 $ VCC);
_EQ008 = cnt00 & cnt01 & cnt02 & !cnt03
# !cnt00 & !cnt01 & cnt02 & !cnt03
# cnt00 & !cnt01 & !cnt02 & !cnt03;
-- Node name is 'out04'
-- Equation name is 'out04', location is LC101, type is output.
out04 = LCELL( _EQ009 $ VCC);
_EQ009 = cnt00 & !cnt01 & !cnt02
# !cnt01 & cnt02 & !cnt03
# cnt00 & !cnt03;
-- Node name is 'out05'
-- Equation name is 'out05', location is LC099, type is output.
out05 = LCELL( _EQ010 $ VCC);
_EQ010 = cnt00 & cnt01 & cnt02 & !cnt03
# !cnt00 & cnt01 & !cnt02 & !cnt03
# cnt00 & !cnt02 & !cnt03;
-- Node name is 'out06'
-- Equation name is 'out06', location is LC097, type is output.
out06 = LCELL( _EQ011 $ !cnt03);
_EQ011 = cnt00 & cnt01 & cnt02 & !cnt03
# !cnt01 & !cnt02;
-- Node name is 'out07'
-- Equation name is 'out07', location is LC094, type is output.
out07 = LCELL( VCC $ VCC);
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information f:\vhdprograme\maichong\maichong.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 4,516K
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