flashctrl_tb.vhd

ＶＨＤＬ编写的flash控制器源代码.包含testbench。

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

--This is a simplified version of Flash Control. Only a subset of flash control is implemented. 
--The following operation are supported:
entity FlashCtrl_TB is
	generic(ADDRESS_WIDTH	: integer range 0 to 32 := 24;
		DATA_WIDTH	: integer range 0 to 16 := 16;
		READ_CYCLES 	: integer range 0 to 15 := 9);
end entity FlashCtrl_TB;

architecture arch1 of FlashCtrl_TB is
component FlashCtrl
	generic(ADDRESS_WIDTH	: integer range 0 to 32 := 24;
		DATA_WIDTH	: integer range 0 to 16 := 16;
		READ_CYCLES 	: integer range 0 to 15 := 9);
	port(
		reset 		: in std_logic; --reset signal. 
		clk 		: in std_logic; --60MHz Clock
	
		--Computer Interface:
		--In 8 bit flash control, the command is 16bit, thus we need 2 wrCmdByte operation to send one command
		CS			: in std_logic;
		wrCmdByte	: in std_logic;
		CmdByte		: in std_logic_vector(7 downto 0);
		
		--test pins:
		wrEPPCmdOut : out std_logic;
		EPPCmdWordOut : out std_logic_vector(15 downto 0);
		
		--
		--Return value to computer
		DataToEPP	: out std_logic_vector(7 downto 0);
		
		--LookupTable Interface:
		rdLUT		: in std_logic;
		LUTAddr		: in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
		LUTData		: out std_logic_vector(DATA_WIDTH-1 downto 0);
		
		--Flash Memory Interface
		FlashAddr 	: out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
		FlashDQ 	: inout std_logic_vector(DATA_WIDTH-1 downto 0);
		CENeg 		: OUT    std_ulogic := 'U';
		OENeg 		: OUT    std_ulogic := 'U';
		WENeg 		: OUT    std_ulogic := 'U';
		RESETNeg 	: OUT    std_ulogic := 'U';
		WPNeg 		: OUT    std_ulogic := 'U'; --WP#/ACC
		BYTENeg 	: OUT    std_ulogic := 'U';
		RY 		: IN   std_ulogic := 'U'  --RY/BY#
	);
end Component;

signal reset : std_logic;
signal clk : std_logic;

signal CS : std_logic;
signal wrCmdByte : std_logic;
signal CmdByte : std_logic_vector(7 downto 0);

signal wrEPPCmdOut : std_logic;
signal EPPCmdWordOut : std_logic_vector(15 downto 0);

signal DataToEPP : std_logic_vector(7 downto 0);

signal rdLUT : std_logic;
signal LUTAddr : std_logic_vector(ADDRESS_WIDTH-1 downto 0);
signal LUTData : std_logic_vector(DATA_WIDTH-1 downto 0);

signal FlashAddr : std_logic_vector(ADDRESS_WIDTH-1 downto 0);
signal FlashDQ : std_logic_vector(DATA_WIDTH-1 downto 0);

signal CENeg, OENeg, WENeg, RESETNeg, WPNeg, BYTENeg : std_logic;
signal RY : std_logic;

signal end_sim : boolean := false;

begin

Inst_FlashCtrl : FlashCtrl
generic map(
	ADDRESS_WIDTH => ADDRESS_WIDTH,
	DATA_WIDTH => DATA_WIDTH,
	READ_CYCLES => READ_CYCLES)
port map(
	reset => reset,
	clk => clk,
	CS => CS,
	wrCmdByte => wrCmdByte,
	CmdByte => CmdByte,
	wrEPPCmdOut => wrEPPCmdOut,
	EPPCmdWordOut => EPPCmdWordOut,
	DataToEPP => DataToEPP,
	rdLUT => rdLUT,
	LUTAddr => LUTAddr,
	LUTData => LUTData,
	FlashAddr => FlashAddr,
	FlashDQ => FlashDQ,
	CENeg => CENeg,
	OENeg => OENeg,
	WENeg => WENeg,
	RESETNeg => RESETNeg,
	WPNeg => WPNeg,
	BYTENeg => BYTENeg,
	RY => RY);
	
	gen_clk: process
	begin
		if end_sim=false then
			clk <= '0';
			wait for 10 ns;
		else
			wait;
		end if;
		if end_sim=false then
			clk <= '1';
			wait for 10 ns;
		else
			wait;
		end if;
	end process;
	
	Stimulus : process
	begin
		reset <= '1';
		wait for 20 ns;
		reset <= '0';
		CS <= '1';
		
		--Write Command Begin
		wait for 20 ns;
		wrCmdByte <= '1';
		CmdByte <= X"10";
		wait for 20 ns;
		cmdByte <= X"50";
		wait for 20 ns;
		wrCmdByte <= '0';
		--Write Command End
	
		--Write Command Begin
		wait for 20 ns;
		wrCmdByte <= '1';
		CmdByte <= X"00";
		wait for 20 ns;
		cmdByte <= X"51";
		wait for 20 ns;
		wrCmdByte <= '0';
		--Write Command End

		--Write Command Begin
		wait for 20 ns;
		wrCmdByte <= '1';
		CmdByte <= X"11";
		wait for 20 ns;
		cmdByte <= X"52";
		wait for 20 ns;
		wrCmdByte <= '0';
		--Write Command End
		
		
		wait for 1 us;
		end_sim <= TRUE;
	end process;
	
end architecture arch1;