📄 flashctrl.vhd
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FlashState <= CHIPRESET;
when others =>
end case;
end if;
FlashStateStatus <= X"01";
when SingleRead =>
--This state is for lookup table
CENeg <= '0';
if wrEPPCmd = '1' and ControlByte = X"10" then
FlashState <= IDLE;
else
case ReadFlashTimer is
when 0 =>
if rdLUT = '1' then
ReadFlashTimer <= 1;
FlashAddr <= LUTAddr;
end if;
when 1 =>
ReadFlashTimer <= 2;
OENeg <= '0';
when 9 =>
LUTData <= FlashDQ;
OENeg <= '1';
ReadFlashTimer <= 0;
when others =>
ReadFlashTimer <= ReadFlashTimer + 1;
end case;
end if;
FlashStateStatus <= X"02";
when BlockRead =>
CENeg <= '0';
case ReadFlashTimer is
when 0 => --In this state, the TargeFlashMemAddr(3 downto 0) should be "0000" because this is a page address
FlashAddr <= TargetFlashMemPageAddr+conv_std_logic_vector(ReadFlashCounter, ADDRESS_WIDTH);
ReadFifoWrreq <= '0';
when 1 =>
OENeg <= '0';
when 9 => --Data is ready, write it to the Flash Memory
OENeg <= '1';
ReadFifoWrreq <= '1';
ReadFifoData(DATA_WIDTH-1 downto 0) <= FlashDQ;
when others =>
end case;
if ReadFlashTimer = 9 then
ReadFlashTimer <= 0;
ReadFlashCounter <= ReadFlashCounter + 1;
else
ReadFlashTimer <= ReadFlashTimer+1;
end if;
if ReadFlashCounter = 16 then
FlashState <= IDLE;
end if;
FlashStateStatus <= X"03";
when BlockWrite => -- use "Write Buffer Programming"
CENeg <= '0';
if WriteTimer < 255 then
WriteTimer <= WriteTimer + 1;
end if;
case WriteTimer is
--1 0x555, 0xAA
when 1 =>
FlashAddr(ADDRESS_WIDTH-1 downto 12) <= (others => '0');
FlashAddr(11 downto 0) <= X"555";
FlashDQ(DATA_WIDTH-1 downto 8) <= (others => '0');
FlashDQ(7 downto 0) <= X"AA";
when 2 =>
WENeg <= '0';
when 6 =>
WENeg <= '1';
--2 0x2AA, 0x55
when 9 =>
FlashAddr(ADDRESS_WIDTH-1 downto 12) <= (others => '0');
FlashAddr(11 downto 0) <= X"2AA";
FlashDQ(DATA_WIDTH-1 downto 8) <= (others => '0');
FlashDQ(7 downto 0) <= X"55";
when 10 =>
WENeg <= '0';
when 14 =>
WENeg <= '1';
--3 SA, 0x25
when 17 =>
FlashAddr <=TargetFlashMemSectorAddr;
FlashDQ(DATA_WIDTH-1 downto 8) <= (others => '0');
FlashDQ(7 downto 0) <= X"25";
when 18 =>
WENeg <= '0';
when 22 =>
WENeg <= '1';
--4 SA, WC(Number of Word - 1)
when 25 =>
FlashAddr <= TargetFlashMemSectorAddr;
FlashDQ <= conv_std_logic_vector(15, DATA_WIDTH);
when 26 =>
WENeg <= '0';
when 30 =>
WENeg <= '1';
--Program Buffer to flash:
when 220 =>
FlashAddr <=TargetFlashMemSectorAddr;
FlashDQ(DATA_WIDTH-1 downto 8) <= (others => '0');
FlashDQ(7 downto 0) <= X"29";
when 221 =>
WENeg <= '0';
when 225 =>
WENeg <= '1';
--Wait for RY valid
when 255 =>
if RY = '1' then
FlashState <= IDLE;
WriteTimer <= 0;
end if;
when others =>
end case;
--when time is between 40 and 400, we begin to program the data from verify fifo into flash fifo
if (WriteTimer > 40) and (WriteFlashCounter < 16) then
if SingleWriteTimer = 9 then
SingleWriteTimer <= 0;
else
SingleWriteTimer <= SingleWriteTimer + 1;
end if;
case SingleWriteTimer is
when 0 =>
WriteFifoRdreq <= '1';
when 1 =>
WriteFifoRdreq <= '0';
FlashAddr <= TargetFlashMemPageAddr + conv_std_logic_vector(WriteFlashCounter, ADDRESS_WIDTH);
FlashDQ <= WriteFifoQ(DATA_WIDTH-1 downto 0);
when 2 =>
WENeg <= '0';
when 6 =>
WENeg <= '1';
when 9 =>
WriteFlashCounter <= WriteFlashCounter + 1;
when others =>
end case;
end if;
FlashStateStatus <= X"04";
when SECTORERASE => --When the system send this command, the sector address need to be sent
--at the same time.
CENeg <= '0';
if WriteTimer < 63 then
WriteTimer <= WriteTimer+1;
end if;
case WriteTimer is
--1 0x555, 0xAA
when 1 =>
FlashAddr(ADDRESS_WIDTH-1 downto 12) <= (others => '0');
FlashAddr(11 downto 0) <= X"555";
FlashDQ(DATA_WIDTH-1 downto 8) <= (others => '0');
FlashDQ(7 downto 0) <= X"AA";
when 2 =>
WENeg <= '0';
when 6 =>
WENeg <= '1';
--2 0x2AA, 0x55
when 9 =>
FlashAddr(ADDRESS_WIDTH-1 downto 12) <= (others => '0');
FlashAddr(11 downto 0) <= X"2AA";
FlashDQ(DATA_WIDTH-1 downto 8) <= (others => '0');
FlashDQ(7 downto 0) <= X"55";
when 10 =>
WENeg <= '0';
when 14 =>
WENeg <= '1';
--3 0x555, 0x80
when 17 =>
FlashAddr(ADDRESS_WIDTH-1 downto 12) <= (others => '0');
FlashAddr(11 downto 0) <= X"555";
FlashDQ(DATA_WIDTH-1 downto 8) <= (others => '0');
FlashDQ(7 downto 0) <= X"80";
when 18 =>
WENeg <= '0';
when 22 =>
WENeg <= '1';
--4 0x555, 0xAA
when 25 =>
FlashAddr(ADDRESS_WIDTH-1 downto 12) <= (others => '0');
FlashAddr(11 downto 0) <= X"555";
FlashDQ(DATA_WIDTH-1 downto 8) <= (others => '0');
FlashDQ(7 downto 0) <= X"AA";
when 26 =>
WENeg <= '0';
when 30 =>
WENeg <= '1';
--5 0x2AA, 0x55
when 33 =>
FlashAddr(ADDRESS_WIDTH-1 downto 12) <= (others => '0');
FlashAddr(11 downto 0) <= X"2AA";
FlashDQ(DATA_WIDTH-1 downto 8) <= (others => '0');
FlashDQ(7 downto 0) <= X"55";
when 34 =>
WENeg <= '0';
when 38 =>
WENeg <= '1';
--6 SA, 0x30
when 41 =>
FlashAddr <= TargetFlashMemSectorAddr;
FlashDQ(DATA_WIDTH-1 downto 8) <= (others => '0');
FlashDQ(7 downto 0) <= X"30";
when 42 =>
WENeg <= '0';
when 46 =>
WENeg <= '1';
when 63 => --Check the status of RY, if '1', the erase complete, return to IDLE
if RY = '1' then
FlashState <= IDLE;
end if;
when others =>
end case;
FlashStateStatus <= X"05";
when CHIPERASE => --When the system send this command, the sector address need to be sent
--at the same time.
if WriteTimer < 63 then
WriteTimer <= WriteTimer+1;
end if;
case WriteTimer is
--1 0x555, 0xAA
when 1 =>
CENeg <= '0';
FlashAddr(ADDRESS_WIDTH-1 downto 12) <= (others => '0');
FlashAddr(11 downto 0) <= X"555";
FlashDQ(DATA_WIDTH-1 downto 8) <= (others => '0');
FlashDQ(7 downto 0) <= X"AA";
when 2 =>
WENeg <= '0';
when 6 =>
WENeg <= '1';
CENeg <= '1';
--2 0x2AA, 0x55
when 9 =>
CENeg <= '0';
FlashAddr(ADDRESS_WIDTH-1 downto 12) <= (others => '0');
FlashAddr(11 downto 0) <= X"2AA";
FlashDQ(DATA_WIDTH-1 downto 8) <= (others => '0');
FlashDQ(7 downto 0) <= X"55";
when 10 =>
WENeg <= '0';
when 14 =>
CENeg <= '1';
WENeg <= '1';
--3 0x555, 0x80
when 17 =>
CENeg <= '0';
FlashAddr(ADDRESS_WIDTH-1 downto 12) <= (others => '0');
FlashAddr(11 downto 0) <= X"555";
FlashDQ(DATA_WIDTH-1 downto 8) <= (others => '0');
FlashDQ(7 downto 0) <= X"80";
when 18 =>
WENeg <= '0';
when 22 =>
CENeg <= '1';
WENeg <= '1';
--4 0x555, 0xAA
when 25 =>
CENeg <= '0';
FlashAddr(ADDRESS_WIDTH-1 downto 12) <= (others => '0');
FlashAddr(11 downto 0) <= X"555";
FlashDQ(DATA_WIDTH-1 downto 8) <= (others => '0');
FlashDQ(7 downto 0) <= X"AA";
when 26 =>
WENeg <= '0';
when 30 =>
CENeg <= '1';
WENeg <= '1';
--5 0x2AA, 0x55
when 33 =>
CENeg <= '0';
FlashAddr(ADDRESS_WIDTH-1 downto 12) <= (others => '0');
FlashAddr(11 downto 0) <= X"2AA";
FlashDQ(DATA_WIDTH-1 downto 8) <= (others => '0');
FlashDQ(7 downto 0) <= X"55";
when 34 =>
WENeg <= '0';
when 38 =>
CENeg <= '1';
WENeg <= '1';
--6 SA, 0x30
when 41 =>
CENeg <= '0';
FlashAddr(ADDRESS_WIDTH-1 downto 12) <= (others => '0');
FlashAddr(11 downto 0) <= X"555";
FlashDQ(DATA_WIDTH-1 downto 8) <= (others => '0');
FlashDQ(7 downto 0) <= X"10";
when 42 =>
WENeg <= '0';
when 46 =>
CENeg <= '1';
WENeg <= '1';
when 63 => --Check the status of RY, if '1', the erase complete, return to IDLE
CENeg <= '0';
if RY = '1' then
FlashState <= IDLE;
end if;
when others =>
end case;
FlashStateStatus <= X"06";
when CHIPRESET =>
-------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------
--Chip Reset Timing Control:
--CHIPRESET: This state is to keep the CHIPRESETNeg for 1us(Because the manual requires at least 500ns), then wait for
--40us(tREADY, 20us min During Embedded Algorithm, 500ns min not during embedded algorithm, we consider
--the worst case), and return to IDLE state.
-------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------
CENeg <= '1';
if WriteTimer < 255 then
WriteTimer <= WriteTimer + 1;
end if;
case WriteTimer is
when 0 =>
ResetNeg <= '0';
when 100 =>
ResetNeg <= '1';
when others =>
end case;
if((RY='1') and (WriteTimer > 200)) then
FlashState <= IDLE;
end if;
FlashStateStatus <= X"07";
end case;
end if;
end process;
end architecture arch1;⌨️ 快捷键说明
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