interlock.v

arm10-behavioral的行为仿真代码ｖｅｒｉｌｏｇＨＤＬ

	    (fill_state == `THIRD_FILL)		|
	    (mispredicted)			|
	    (dabort | dabort_1)			|
	    (fill_state == `FIRST_MISPREDICT)	|
	    (fill_state == `SECOND_MISPREDICT))
		me_enbar = 1'b1;
	else
		me_enbar = 1'b0;
    end

//The WB stage can be squashed if:
//1) Load PC from Memory
//2) Pipeline is being refilled
//3) Data Abort
always @(load_pc_latch or fill_state or dabort or dabort_1)
    begin
	if ((load_pc_latch)||
	    (fill_state == `THIRD_FILL)		|
	    (fill_state == `FIRST_MISPREDICT)	|
	    (fill_state == `SECOND_MISPREDICT)	|
	    (fill_state == `THIRD_MISPREDICT)	|
	    (dabort | dabort_1))
		wb_enbar = 1'b1;
	else
		wb_enbar = 1'b0;
    end

/*------------------------------------------------------------------------
         Sequential Always Blocks (Latches)
------------------------------------------------------------------------*/
//It is time to begin refilling the pipeline.
wire TCLK = (TESTMODE) ? nGCLK : ~nGCLK;
//synopsys async_set_reset "nRESET"
always @(posedge TCLK or negedge nRESET)
  begin
    if (~nRESET)
      nRefill <= 1'b0;
    else
      nRefill <= ~(pc_modified | load_pc | ~delayed_reset) | mispredicted;
  end

//Latch the Coprocessor Handshake signals.  If its the first
//cycle of the coprocessor inst, should be latching CHSD, else CHSE
//synopsys async_set_reset "nRESET"
always @(posedge TCLK or negedge nRESET)
    begin
	if (!nRESET)
	    latched_chs <= 2'h3;		//Last
	else if ((~if_enbar & ~cop_not_first) | (cop_not_first))
	    latched_chs <= (cop_not_first) ? CHSE : CHSD;
    end

//Create a Latch that will Start the Coprocessor Counter
//synopsys async_set_reset "nRESET"
always @(nGCLK or cop_count or cop_not_first or nRESET)
    begin
	if (!nRESET)
	    start_count <= 1'b0;
	else if (~nGCLK)
	    start_count <= cop_count & !cop_not_first;
    end   

//Create a FF that will Remember that the PC was loaded from
//Memory...thus requiring an extra bubble in the pipeline.
//synopsys async_set_reset "nRESET"
always @(posedge nGCLK or negedge nRESET)
    begin
	if (!nRESET)
	    load_pc_latch <= 1'b0;
	else
	    load_pc_latch <= load_pc;
    end

//This block normally catches a bubble due to a prediction
//and keeps the bubble from fouling up the Ex Stage
//Added in the if_enbar so that if id and if are waiting (for LDM/STM)
//ex_enbar doesn't go high until after the ID bubble is present.
//synopsys async_set_reset "nRESET"
//Added in the fill_state because can predict a branch while pipe is
//refilling, in which case, ex_enbar may be high, so still need to
//capture the stall.
//Added in pt & ps & if_en so that if ptaken_ex is still high, you 
//can still stall the next cycle (this may happen in an every-other
//patter with prediction stalls) dO24.18713
wire ptaken_disable = ~(~ex_enbar | (fill_state == `SECOND_FILL & nRefill) |
                (ptaken_ex & prediction_stall & ~if_enbar));
//synopsys async_set_reset "nRESET"
always @(posedge nGCLK or negedge nRESET)
  begin 
    if (~nRESET)
      ptaken_ex <= 1'b0;
    else if (~ptaken_disable)
      ptaken_ex <= prediction_stall & ~if_enbar;
    else if (~hold_next_ex)
      ptaken_ex <= 1'b0;
  end

//This block determines that a two-cycle inst is being stalled for
//some other reason, than its the first
//synopsys async_set_reset "nRESET"
always @(posedge nGCLK or negedge nRESET)
  begin
    if (~nRESET)
      third_plus <= 1'b0;      
    else
      third_plus <= (need_2cycles & second & id_enbar) |
		    (need_2cycles & third_plus & id_enbar);
  end

/*------------------------------------------------------------------------
         FSM Next State Logic
------------------------------------------------------------------------*/

//Fill FSM
always @(fill_state or mispredicted or misp_rec)
    begin 
	case (fill_state) //synopsys full_case parallel_case
	    `IDLE: begin
		    if (misp_rec) 
			next_fill_state = `SECOND_MISPREDICT;
		    else if (mispredicted)
			next_fill_state = `FIRST_MISPREDICT;
		    else 
			next_fill_state = `IDLE;
		  end

	    `FIRST_FILL: next_fill_state = `SECOND_FILL;
	    `SECOND_FILL: next_fill_state = `THIRD_FILL;
	    `THIRD_FILL: next_fill_state = `IDLE;
	    `FOURTH_FILL: next_fill_state = `IDLE;
	    `FIRST_MISPREDICT: next_fill_state = `SECOND_MISPREDICT;
	    `SECOND_MISPREDICT: next_fill_state = `THIRD_MISPREDICT;
	    `THIRD_MISPREDICT: begin
                                if (misp_rec)
                                  next_fill_state = `SECOND_MISPREDICT;
                                else if (mispredicted)
                                  next_fill_state = `FIRST_MISPREDICT;
                                else
                                  next_fill_state = `IDLE;
                              end
	    
	endcase
    end

//Coprocessor Cycle Count Next State Logic
always @(cop_cyc_count or cop_count)
    begin
	case (cop_cyc_count) //synopsys full_case parallel_case
	    `NO_COUNT: next_cyc_count = `NO_COUNT;

	    `SECOND_CYCLE: 
		   next_cyc_count = (cop_count) ? `THIRD_CYCLE
						: `NO_COUNT; 

	    `THIRD_CYCLE:
                   next_cyc_count = (cop_count) ? `FOURTH_PLUS_CYCLE 
						: `NO_COUNT;
	    `FOURTH_PLUS_CYCLE:
		   next_cyc_count = (cop_count) ? `FOURTH_PLUS_CYCLE
						: `NO_COUNT;
	endcase
    end


/*------------------------------------------------------------------------
         FSM Registers
------------------------------------------------------------------------*/

//Fill FSM
wire nFillReset = (TESTMODE) ? 1'b1 : nRefill;

//synopsys async_set_reset "nFillReset"
always @(negedge nFillReset or posedge nGCLK)
    begin
	if (~nFillReset)
	    fill_state <= `SECOND_FILL;
	else if (!load_pc)
	    fill_state <= next_fill_state;
    end
/*
always @(negedge nRefill or posedge nGCLK)
  begin
    if (~nRefill)
      fill_state[0] <= 1'b1;
    else
      fill_state[0] <= next_fill_state[0];
  end
always @(negedge nRefill or posedge nGCLK)
  begin
    if (~nRefill)
      fill_state[1] <= 1'b0;
    else
      fill_state[1] <= next_fill_state[1];
  end
always @(negedge nRefill or posedge nGCLK)
  begin
    if (~nRefill)
      fill_state[2] <= 1'b0;
    else
      fill_state[2] <= next_fill_state[2];
  end
*/
//Count FSM
//synopsys async_set_reset "nRESET"
always @(posedge nGCLK or negedge nRESET)
    begin
	if (!nRESET)
	    cop_cyc_count <= `NO_COUNT;
	else if (~id_enbar)
	  begin
	    if (start_count)
	      cop_cyc_count <= `SECOND_CYCLE;
	    else
	      cop_cyc_count <= next_cyc_count;
	  end
    end

//This block captures the nRESET signal
//synopsys async_set_reset "nRESET"
always @(negedge nRESET or posedge nGCLK)
    begin
      if (!nRESET)
          latched_reset <= 1'b0;  
      else
          latched_reset <= 1'b1;
    end

always @(posedge nGCLK or negedge nRESET)
  begin
    if (~nRESET)
      delayed_reset <= 1'b0;
    else
      delayed_reset <= latched_reset;
  end

//This block catures the dabort signal
//synopsys async_set_reset "nRESET"
always @(posedge nGCLK or negedge nRESET)
    begin
	if (!nRESET)
	    dabort_1 <= 1'b0;
	else
	    dabort_1 <= dabort;
    end

endmodule