ram.v

arm10-behavioral的行为仿真代码ｖｅｒｉｌｏｇＨＤＬ

`timescale 1ns/10ps
/*****************************************************************************
$RCSfile: ram.v,v $
$Revision: 1.3 $
$Author: kohlere $
$Date: 2000/03/23 18:26:19 $
$State: Exp $
$Source: &

Description:  Cache Memory Module

*****************************************************************************/

module ram (nGCLK, write_sel, read_sel, write_port, read_port, wr_ena);

parameter	LSS = 2;	//Line Select Bits
parameter       NL = 4;         //Number of Cache Lines (kB = 32*NL/1024)

/*------------------------------------------------------------------------
        Ports
------------------------------------------------------------------------*/

input	[255:0]		write_port;	//Write Value
input 	[LSS-1:0]	read_sel;	//Read Select Line
input	[LSS-1:0]	write_sel;	//Write Select Line
input			nGCLK;		//Clock Signal
input			wr_ena;		//Write Enable

output	[255:0]		read_port;	//Read Line

/*------------------------------------------------------------------------
        Signal Declarations
------------------------------------------------------------------------*/

reg	[255:0]	mem	[NL-1:0];	//Memory Declaration
wire	[255:0]	read_port;		//Read Port

//synopsys translate_off
assign #2 read_port = mem[read_sel];

always @(posedge nGCLK)
  begin
    if (wr_ena)
      mem[write_sel] <= #1 write_port;
  end
//synopsys translate_on

endmodule