wb.v

arm10-behavioral的行为仿真代码ｖｅｒｉｌｏｇＨＤＬ

/*****************************************************************************
$RCSfile: wb.v,v $
$Revision: 1.2 $
$Author: kohlere $
$Date: 2000/02/03 18:16:30 $
$State: Exp $
$Source: /home/lefurgy/tmp/ISC-repository/isc/hardware/ARM10/behavioral/pipelined/wb.v,v $
                
Description: This is the Write Back Stage.  It performs all writes to the
		register file. 

*****************************************************************************/

module wb(GCLK, nRESET, wb_enbar, base, me_result,
		write_Rd_me, write_Rn_me, Rd_me, Rn_me, 
		rfw_ena_a, rfw_ena_b, write_a, write_b,
		Rd_wb, Rn_wb, write_Rd_wb, write_Rn_wb);

/*------------------------------------------------------------------------
        Ports
------------------------------------------------------------------------*/

input	[31:0]	base;			//Value to Write to Base
input	[31:0]	me_result;		//Value to Write to Rd
input	[4:0]	Rd_me;			//1st Destination Register
input	[4:0]	Rn_me;			//2nd Destination Register
input		GCLK;			//Clock Signal
input		nRESET;			//Reset Signal
input		wb_enbar;		//WB Stage Enable
input		write_Rd_me;		//Cond Failed?
input		write_Rn_me;		//WB the base?

output	[31:0]	write_a;		//A data to RF
output	[31:0]	write_b;		//B data to RF
output	[4:0]	Rd_wb;			//Destination Register
output	[4:0]	Rn_wb;			//Base Register
output		rfw_ena_a;		//Enable Write to Port A
output		rfw_ena_b;		//Enable Write to Port B
output		write_Rd_wb;		//WB the destination?
output		write_Rn_wb;		//WB the base?

/*------------------------------------------------------------------------
        Variable Declarations
------------------------------------------------------------------------*/

//Declare Output of Multiplexers and Regiseters
reg	[31:0]	base_reg;		//Base Value to Write Back
reg	[31:0]	wb_result;		//Value to Write to Rd
reg	[4:0]	Rd_wb;			//1st Destination Register
reg	[4:0]	Rn_wb;			//2nd Destination Register
reg		write_Rd_wb;		//Write to Rd?
reg		write_Rn_wb;		//Write to Rn?

//Declare Output of Combinational Logic
wire	[31:0]	write_a;		//Data to Port A
wire	[31:0]	write_b;		//Data to Port B
wire		rfw_ena_a;		//Enable Port A
wire		rfw_ena_b;		//Enable Port B
wire		reset_ena;		//Reset the Enable Signal

/*------------------------------------------------------------------------
        Basic Assignments (Combinational Logic)
------------------------------------------------------------------------*/

assign write_a = wb_result;
assign write_b = base_reg;
assign rfw_ena_a = (write_Rd_wb) ? 1'b1 : 1'b0;
assign rfw_ena_b = (write_Rn_wb) ? 1'b1 : 1'b0;
assign reset_ena = (GCLK & (rfw_ena_a | rfw_ena_b) | !nRESET);

/*------------------------------------------------------------------------
        Sequential Always Blocks (Registers)
------------------------------------------------------------------------*/

//This block controls the base_reg latch
always @(negedge GCLK or negedge nRESET)
    begin
        if (!nRESET)
            base_reg <= 32'h00000000;
        else if (!wb_enbar)
            base_reg <= base;
    end

//This block controls the wb_result latch
always @(negedge GCLK or negedge nRESET)
    begin
        if (!nRESET)
            wb_result <= 32'h00000000;
        else if (!wb_enbar)
            wb_result <= me_result;
    end

//This block controls the Rd_wb latch
always @(negedge GCLK or negedge nRESET)
    begin
        if (!nRESET)
            Rd_wb <= 5'h00;
        else if (!wb_enbar)
            Rd_wb <= Rd_me;
    end

//This block controls the Rn_wb latch
always @(negedge GCLK or negedge nRESET)
    begin
        if (!nRESET)
            Rn_wb <= 5'h00;       
        else if (!wb_enbar)
            Rn_wb <= Rn_me;    
    end

//This block controls the cond_failed_wb latch
always @(negedge GCLK or posedge reset_ena)
    begin
        if (reset_ena)
            write_Rd_wb <= 1'h0;
        else if (wb_enbar)
	    write_Rd_wb <= 1'b0;
	else if (!wb_enbar)
            write_Rd_wb <= write_Rd_me;
    end

//This block controls the w_wb latch
always @(negedge GCLK or posedge reset_ena)
    begin
        if (reset_ena)
            write_Rn_wb <= 1'h0;
        else if (wb_enbar)
	    write_Rn_wb <= 1'h0;
	else if (!wb_enbar)
            write_Rn_wb <= write_Rn_me;
    end

/*======================================================================*/
endmodule       //wb
/*======================================================================*/