testarm.v

arm10-behavioral的行为仿真代码ｖｅｒｉｌｏｇＨＤＬ

`timescale 1ns/10ps
`define unit_delay 1

module test_arm();

reg	[1:0]	TESTSELECT;
reg		TESTMODE;
reg		TEST_SI;
reg 		GCLK;
reg 		nRESET;
reg 		nFIQ;
reg 		nIRQ;
reg 		ISYNC;

wire 		ECLK;
wire		TEST_SO;
wire	[31:0]	MMA;
wire	[31:0]	MMD;
wire		MCLK;
wire		MMnWR;
wire		DRIVE_MMD_OFFCHIP;

arm9 xarm9(.nRESET(nRESET), .GCLK(GCLK), .ECLK(ECLK),
                .nFIQ(nFIQ), .nIRQ(nIRQ), .ISYNC(ISYNC),
                .TESTMODE(TESTMODE), .TESTSELECT(TESTSELECT),
                .TEST_SI(TEST_SI), .TEST_SO(TEST_SO),
                .MMA(MMA), .MMD(MMD), .MMnWR(MMnWR),
                .MCLK(MCLK), .DRIVE_MMD_OFFCHIP(DRIVE_MMD_OFFCHIP));

//mainmem xmainmem(.MMA(MMA), .MMD(MMD), .GCLK(MCLK), .MMnWR(MMnWR));

initial
begin
	nRESET=1'b0;
	nIRQ=1'b1;
	nFIQ=1'b1;
	ISYNC=1'b1;
	GCLK=1'b1;
	TESTMODE = 1'b0;
	TESTSELECT = 2'h0;
        TEST_SI = 1'b0;
//	$readmemh("arm-compress-little.vhx",xarm9.xmainmem.xmem1.memory);
	$readmemh("testarm.vhx",xarm9.xmainmem.xmem1.memory);
	//Comment Out Next Two line for Checker
	$recordfile("arm.trn");
	$recordvars;
	#61 
	nRESET = 1'b1;

/* Back Annotations */
/*
$sdf_annotate("regfile.sdf",xarm.xarm9.xrf,,"rf.sdflog");
$sdf_annotate("pipe.sdf",xarm.xarm9.xpipe,,"pipe.sdflog");
$sdf_annotate("control.sdf",xarm.xarm9.xcontrol,,"control.sdflog");
$sdf_annotate("mmu.sdf",xarm.xarm9.xmmu,,"mmu.sdflog");
$sdf_annotate("dcache.sdf",xarm.xarm9.xdcache1,,"dcache.sdflog");
$sdf_annotate("icache.sdf",xarm.xarm9.xicache1,,"icache.sdflog");
$sdf_annotate("arm9.sdf",xarm,,"arm9.sdflog");
*/

end


always #10 GCLK = ~GCLK;

//I use this section to catch the end of programs.
//and stop the simulator.  Comment Out for Checker

//This prevents an infinite loop.A
always #40000 $finish;


endmodule