arm9.v

arm10-behavioral的行为仿真代码ｖｅｒｉｌｏｇＨＤＬ

      DRIVE_MMD_OFFCHIP <= #1 drive_mmd;
  end

icache	xicache1 (.nGCLK(gclk5), .nRESET(nRESET), .IA(IA),
		  .ID(ID), .imiss(imiss), .InMREQ(InMREQ | ~nreset), 
		  .MMD(MMD), .imiss_addr(imiss_addr),
		  .mmd_valid(ic_read_mmd), .newline(newline),
		  .dmiss(dmiss), .doublehold(doublehold),
		  .IABORT(IABORT), .useMini(useMini), .DABORT(DABORT),
		  .swic(iswic), .swic_data(swic_data), 
		  .swic_addr(store_addr[31:2]), .initializing(ic_init));
//modified the swic_addr from swic_addr to DA...now address coming from ARM

dcache  xdcache1 (.nGCLK(gclk5), .nRESET(nRESET), .DA(store_addr),
                  .DD(data_bus_me), .dmiss(dmiss), .DnMREQ(DnMREQ),
                  .MMD(MMD), .dmiss_addr(dmiss_addr), .DMAS(DMAS),
                  .mmd_valid(dc_read_mmd), .dwb(dwb), .MMnWR(MMnWR),
		  .drive_mmd(drive_mmd), .DnWR(DnWR), .DABORT(DABORT),
		  .BIGEND(BIGEND), .istall(istall), .swic(dswic),
		  .swic_data(swic_data),
		  .doublehold(doublehold), .initializing(dc_init),
		  .data_decomp(data_decomp), .flush(dflush));

//synopsys translate_off
mainmem xmainmem(.MMA(MMA), .MMD(MMD), .GCLK(gclk5), .MMnWR(MMnWR));
/*------------------------------------------------------------------------
        Register File
------------------------------------------------------------------------*/
wire 	[31:0] 	r0, r1, r2, r3,		//Declare 31, 32-bit registers
		r4, r5, r6, r7,
		r8, r9, r10, r11,
		r12, r13, r14,
		r16, r17, r18, r19,
		r20, r21, r22, r23,
		r24, r25, r26, r27,
		r28, r29, r30;

assign r0 = xrf.r0;
assign r1 = xrf.r1;
assign r2 = xrf.r2;
assign r3 = xrf.r3;
assign r4 = xrf.r4;
assign r5 = xrf.r5;
assign r6 = xrf.r6;
assign r7 = xrf.r7;
assign r8 = xrf.r8;
assign r9 = xrf.r9;
assign r10 = xrf.r10;
assign r11 = xrf.r11;
assign r12 = xrf.r12;
assign r13 = xrf.r13;
assign r14 = xrf.r14;
assign r16 = xrf.r16;
assign r17 = xrf.r17;
assign r18 = xrf.r18;
assign r19 = xrf.r19;
assign r20 = xrf.r20;
assign r21 = xrf.r21;
assign r22 = xrf.r22;
assign r23 = xrf.r23;
assign r24 = xrf.r24;
assign r25 = xrf.r25;
assign r26 = xrf.r26;
assign r27 = xrf.r27;
assign r28 = xrf.r28;
assign r29 = xrf.r29;
assign r30 = xrf.r30;

reg     [31:0]  cpsr;
reg     [31:0]  spsr_und;
reg     [31:0]  spsr_abt;
reg     [31:0]  spsr_fiq;
reg     [31:0]  spsr_irq;
reg     [31:0]  spsr_svc;

wire 	[31:0] r15 = pc_if;		//Set R15 = PC

initial
begin
        xrf.r0 = 32'h00000000;
        xrf.r1 = 32'h00000000;
        xrf.r2 = 32'h00000000;
        xrf.r3 = 32'h00000000;
        xrf.r4 = 32'h00000000;
        xrf.r5 = 32'h00000000;
        xrf.r6 = 32'h00000000;
        xrf.r7 = 32'h00000000;
        xrf.r8 = 32'h00000000;
        xrf.r9 = 32'h00000000;
        xrf.r10 = 32'h00000000;
        xrf.r11 = 32'h00000000;
        xrf.r12 = 32'h00000000;
        xrf.r13 = 32'h00000000;
        xrf.r14 = 32'h00000000;
        xrf.r16 = 32'h00000000;
        xrf.r17 = 32'h00000000;
        xrf.r18 = 32'h00000000;
        xrf.r19 = 32'h00000000;
        xrf.r20 = 32'h00000000;
        xrf.r21 = 32'h00000000;
        xrf.r22 = 32'h00000000;
        xrf.r23 = 32'h00000800;
        xrf.r24 = 32'h00000000;
        xrf.r25 = 32'h00000800;
        xrf.r26 = 32'h00000000;
        xrf.r27 = 32'h00000000;
        xrf.r28 = 32'h00000000;
        xrf.r29 = 32'h00000800;
        xrf.r30 = 32'h00000000;
	cpsr = 32'h00000010;
	spsr_svc = 32'h00000000;
        spsr_fiq = 32'h00000000;
        spsr_irq = 32'h00000000;
        spsr_abt = 32'h00000000;
        spsr_und = 32'h00000000;
	xpipe.xex.CPSR=32'h00000010;
	xpipe.xex.spsr_svc=32'h0;
	xpipe.xex.spsr_und=32'h0;
	xpipe.xex.spsr_abt=32'h0;
	xpipe.xex.spsr_fiq=32'h0;
	xpipe.xex.spsr_irq=32'h0;
        xpipe.xex.Rn_ex = 5'h00;
        xpipe.xex.Rd_ex = 5'h00;
	xpipe.xex.inst_type_ex = 4'h0;
end

/*------------------------------------------------------------------------
        Cache Coherence Protocol (Behavioral)
------------------------------------------------------------------------*/
//Only necessary because random programs sometimes exhibit
//self-modifying code.  Prohibited normally.
//Also for watching the store actions, if a line is valid
//in the cache, look at it, rather than main memory because
//main memory may be stale.

/* Everything In here assumes Both Caches the Same Size */

parameter       WPL = 8;        //Words Per Cache Line (Don't Change!)
parameter       LS = WPL*32;    //Line Size (Don't Change!)

parameter       NL = 512;       //Number of Cache Lines (kB = 32*NL/1024)
parameter       LSS = 9;        //Line Select Bits = Log2(NL)

parameter       LSH = LSS + 4;  //LS High Bit Add = <Tag><LSS><word><byte>
parameter       PSL = LSH + 1;  //Page Select Low Bit
parameter       TS=2+(32-PSL);  //Tag Size D,V,Page Select
parameter       TH=TS-1;        //Tag High Bit Value
parameter       PSH = TH-2;     //Page Select High Bit Value

reg [TH:0] tag_temp;
reg [TH:0] dtag_temp;
reg [255:0] cline_temp;
reg [255:0] cline_temp2;
reg store_me, store_wb, double_wb;
reg	flag;
reg     doin_coherence;

reg got;
always @(negedge eclk24)
  begin
    if ((addr_bus_me >= 32'h00003bc0) && (addr_bus_me < 32'h00003be0))
      got = 1'b1;
    else
      got = 1'b0;
  end

always @(posedge eclk24)
  begin
    #8;
    tag_temp = xicache1.xitag.tag[addr_bus[LSH:5]];
    dtag_temp = xdcache1.xdtag.tag[IA[LSH:5]];
    cline_temp = xdcache1.xdcache.mem[addr_bus[LSH:5]];
    cline_temp2 = xdcache1.xdcache.mem[IA[LSH:5]];
    if ((tag_temp[TH-1:0] === {1'b1,addr_bus[31:PSL]}) & store_wb)
      begin
        xicache1.xitag.tag[addr_bus[LSH:5]] <= #1 {2'b00,tag_temp[PSH:0]};
	case(addr_bus[4:2])
            3'h0: begin
        xmainmem.xmem1.mem1[addr_bus[18:2]]={1'b0,cline_temp[7:0]};
	xmainmem.xmem1.mem2[addr_bus[18:2]]={1'b0,cline_temp[15:8]};
	xmainmem.xmem1.mem3[addr_bus[18:2]]={1'b0,cline_temp[23:16]};
	xmainmem.xmem1.mem4[addr_bus[18:2]]={1'b0,cline_temp[31:24]};
                  end
            3'h1: begin
        xmainmem.xmem1.mem1[addr_bus[18:2]]={1'b0,cline_temp[39:32]};  
        xmainmem.xmem1.mem2[addr_bus[18:2]]={1'b0,cline_temp[47:40]}; 
        xmainmem.xmem1.mem3[addr_bus[18:2]]={1'b0,cline_temp[55:48]};
        xmainmem.xmem1.mem4[addr_bus[18:2]]={1'b0,cline_temp[63:56]};
                  end
            3'h2: begin
        xmainmem.xmem1.mem1[addr_bus[18:2]]={1'b0,cline_temp[71:64]};  
        xmainmem.xmem1.mem2[addr_bus[18:2]]={1'b0,cline_temp[79:72]}; 
        xmainmem.xmem1.mem3[addr_bus[18:2]]={1'b0,cline_temp[87:80]};
        xmainmem.xmem1.mem4[addr_bus[18:2]]={1'b0,cline_temp[95:88]};
                  end
            3'h3: begin
        xmainmem.xmem1.mem1[addr_bus[18:2]]={1'b0,cline_temp[103:96]};  
        xmainmem.xmem1.mem2[addr_bus[18:2]]={1'b0,cline_temp[111:104]}; 
        xmainmem.xmem1.mem3[addr_bus[18:2]]={1'b0,cline_temp[119:112]};
        xmainmem.xmem1.mem4[addr_bus[18:2]]={1'b0,cline_temp[127:120]};
                  end
            3'h4: begin
        xmainmem.xmem1.mem1[addr_bus[18:2]]={1'b0,cline_temp[135:128]};  
        xmainmem.xmem1.mem2[addr_bus[18:2]]={1'b0,cline_temp[143:136]}; 
        xmainmem.xmem1.mem3[addr_bus[18:2]]={1'b0,cline_temp[151:144]};
        xmainmem.xmem1.mem4[addr_bus[18:2]]={1'b0,cline_temp[159:152]};
                  end
            3'h5: begin
        xmainmem.xmem1.mem1[addr_bus[18:2]]={1'b0,cline_temp[167:160]};  
        xmainmem.xmem1.mem2[addr_bus[18:2]]={1'b0,cline_temp[175:168]}; 
        xmainmem.xmem1.mem3[addr_bus[18:2]]={1'b0,cline_temp[183:176]};
        xmainmem.xmem1.mem4[addr_bus[18:2]]={1'b0,cline_temp[191:184]};
                  end
            3'h6: begin
        xmainmem.xmem1.mem1[addr_bus[18:2]]={1'b0,cline_temp[199:192]};  
        xmainmem.xmem1.mem2[addr_bus[18:2]]={1'b0,cline_temp[207:200]}; 
        xmainmem.xmem1.mem3[addr_bus[18:2]]={1'b0,cline_temp[215:208]};
        xmainmem.xmem1.mem4[addr_bus[18:2]]={1'b0,cline_temp[223:216]};
                  end
            3'h7: begin
        xmainmem.xmem1.mem1[addr_bus[18:2]]={1'b0,cline_temp[231:224]};  
        xmainmem.xmem1.mem2[addr_bus[18:2]]={1'b0,cline_temp[239:232]}; 
        xmainmem.xmem1.mem3[addr_bus[18:2]]={1'b0,cline_temp[247:240]};
        xmainmem.xmem1.mem4[addr_bus[18:2]]={1'b0,cline_temp[255:248]};
                  end
        endcase
        flag = 1'b1;
      end
    else flag = 1'b0;

    if (dtag_temp === {2'h3,IA[31:PSL]})
      begin
        case(IA[4:2])
            3'h0: begin
        xmainmem.xmem1.mem1[IA[18:2]]={1'b0,cline_temp2[7:0]};   
        xmainmem.xmem1.mem2[IA[18:2]]={1'b0,cline_temp2[15:8]};   
        xmainmem.xmem1.mem3[IA[18:2]]={1'b0,cline_temp2[23:16]};  
        xmainmem.xmem1.mem4[IA[18:2]]={1'b0,cline_temp2[31:24]};  
                  end
            3'h1: begin
        xmainmem.xmem1.mem1[IA[18:2]]={1'b0,cline_temp2[39:32]};  
        xmainmem.xmem1.mem2[IA[18:2]]={1'b0,cline_temp2[47:40]};  
        xmainmem.xmem1.mem3[IA[18:2]]={1'b0,cline_temp2[55:48]};  
        xmainmem.xmem1.mem4[IA[18:2]]={1'b0,cline_temp2[63:56]};  
                  end
            3'h2: begin
        xmainmem.xmem1.mem1[IA[18:2]]={1'b0,cline_temp2[71:64]};  
        xmainmem.xmem1.mem2[IA[18:2]]={1'b0,cline_temp2[79:72]};  
        xmainmem.xmem1.mem3[IA[18:2]]={1'b0,cline_temp2[87:80]};  
        xmainmem.xmem1.mem4[IA[18:2]]={1'b0,cline_temp2[95:88]};  
                  end
            3'h3: begin
        xmainmem.xmem1.mem1[IA[18:2]]={1'b0,cline_temp2[103:96]}; 
        xmainmem.xmem1.mem2[IA[18:2]]={1'b0,cline_temp2[111:104]};
        xmainmem.xmem1.mem3[IA[18:2]]={1'b0,cline_temp2[119:112]};
        xmainmem.xmem1.mem4[IA[18:2]]={1'b0,cline_temp2[127:120]};
                  end
            3'h4: begin
        xmainmem.xmem1.mem1[IA[18:2]]={1'b0,cline_temp2[135:128]};
        xmainmem.xmem1.mem2[IA[18:2]]={1'b0,cline_temp2[143:136]};
        xmainmem.xmem1.mem3[IA[18:2]]={1'b0,cline_temp2[151:144]};
        xmainmem.xmem1.mem4[IA[18:2]]={1'b0,cline_temp2[159:152]};
                  end
            3'h5: begin
        xmainmem.xmem1.mem1[IA[18:2]]={1'b0,cline_temp2[167:160]};
        xmainmem.xmem1.mem2[IA[18:2]]={1'b0,cline_temp2[175:168]};
        xmainmem.xmem1.mem3[IA[18:2]]={1'b0,cline_temp2[183:176]};
        xmainmem.xmem1.mem4[IA[18:2]]={1'b0,cline_temp2[191:184]};
                  end
            3'h6: begin
        xmainmem.xmem1.mem1[IA[18:2]]={1'b0,cline_temp2[199:192]};
        xmainmem.xmem1.mem2[IA[18:2]]={1'b0,cline_temp2[207:200]};
        xmainmem.xmem1.mem3[IA[18:2]]={1'b0,cline_temp2[215:208]};
        xmainmem.xmem1.mem4[IA[18:2]]={1'b0,cline_temp2[223:216]};
                  end  
            3'h7: begin
        xmainmem.xmem1.mem1[IA[18:2]]={1'b0,cline_temp2[231:224]};
        xmainmem.xmem1.mem2[IA[18:2]]={1'b0,cline_temp2[239:232]};
        xmainmem.xmem1.mem3[IA[18:2]]={1'b0,cline_temp2[247:240]};
        xmainmem.xmem1.mem4[IA[18:2]]={1'b0,cline_temp2[255:248]};
                  end  
        endcase
        doin_coherence = 1'b1;
      end
    else
      doin_coherence = 1'b0;
  end

/*------------------------------------------------------------------------
        Checker Stuff to keep it thinking everything is OK
------------------------------------------------------------------------*/

//Make CPSR/SPSR updates look like they're happening in WB stage
always @(posedge eclk24)
    begin
	cpsr <= xpipe.xex.CPSR;
	spsr_und <= xpipe.xex.spsr_und;
	spsr_abt <= xpipe.xex.spsr_abt;
	spsr_irq <= xpipe.xex.spsr_irq;
	spsr_fiq <= xpipe.xex.spsr_fiq;
	spsr_svc <= xpipe.xex.spsr_svc;
    end

//Make ld/st look like they're happening in WB stage
reg [255:0] line_temp;
reg [8:0] tb1, tb2, tb3, tb4;
always @(posedge eclk24 or negedge nRESET)
    begin
	if (!nRESET)
	  begin
	    store_me <= 1'b0;
	    store_wb <= 1'b0;
	    double_wb <= 1'b0;
	    addr_bus_me <= 32'h00000000;
	    addr_bus <= 32'h00000000;
	  end
	else
	  begin
	    store_me <= ~DnMREQ & store_ex;
	    store_wb <= store_me;
	    double_wb <= double_me;
	    addr_bus_me <= store_addr;
	    addr_bus <= addr_bus_me;
	  end
    end

always @(posedge eclk24)
    begin
	#3;
	if (store_wb)
	  begin
	    if (double_wb)
	      begin
		if (xdcache1.xdtag.tag[addr_bus[LSH:5]] == {2'h3,addr_bus[31:PSL]})
		  begin
		    line_temp = xdcache1.xdcache.mem[addr_bus[LSH:5]];
		    case (addr_bus[4:2])
		      3'h0: data_bus = line_temp[31:0];
		      3'h1: data_bus = line_temp[63:32];
                      3'h2: data_bus = line_temp[95:64];
		      3'h3: data_bus = line_temp[127:96];
                      3'h4: data_bus = line_temp[159:128];
                      3'h5: data_bus = line_temp[191:160];
		      3'h6: data_bus = line_temp[223:192];
		      3'h7: data_bus = line_temp[255:224];
                    endcase
		  end
	        else
                  begin
		    tb1 = xmainmem.xmem1.mem1[addr_bus_me[18:2]];
		    tb2 = xmainmem.xmem1.mem2[addr_bus_me[18:2]];
 		    tb3 = xmainmem.xmem1.mem3[addr_bus_me[18:2]];
		    tb4 = xmainmem.xmem1.mem4[addr_bus_me[18:2]];
		    data_bus = {tb4[7:0],tb3[7:0],tb2[7:0],tb1[7:0]};
		  end
		//$save_store();
	       
		addr_bus = addr_bus + 4;
                if (xdcache1.xdtag.tag[addr_bus[LSH:5]] == {2'h3,addr_bus[31:PSL]})
		  begin
                    line_temp = xdcache1.xdcache.mem[addr_bus[LSH:5]];
                    case (addr_bus[4:2])
                      3'h0: data_bus = line_temp[31:0];
                      3'h1: data_bus = line_temp[63:32];
                      3'h2: data_bus = line_temp[95:64];
                      3'h3: data_bus = line_temp[127:96];
                      3'h4: data_bus = line_temp[159:128];
                      3'h5: data_bus = line_temp[191:160];
                      3'h6: data_bus = line_temp[223:192];
                      3'h7: data_bus = line_temp[255:224];
                    endcase
                  end
                else 
                  begin
                    tb1 = xmainmem.xmem1.mem1[addr_bus_me[18:2]];
                    tb2 = xmainmem.xmem1.mem2[addr_bus_me[18:2]];
                    tb3 = xmainmem.xmem1.mem3[addr_bus_me[18:2]];
                    tb4 = xmainmem.xmem1.mem4[addr_bus_me[18:2]];
                    data_bus = {tb4[7:0],tb3[7:0],tb2[7:0],tb1[7:0]};
                  end
                //$save_store();
	      end
	    else
	      begin
                if (xdcache1.xdtag.tag[addr_bus[LSH:5]] == {2'h3,addr_bus[31:PSL]})
		  begin
                    line_temp = xdcache1.xdcache.mem[addr_bus[LSH:5]];
                    case (addr_bus[4:2])
                      3'h0: data_bus = line_temp[31:0]; 
                      3'h1: data_bus = line_temp[63:32];
                      3'h2: data_bus = line_temp[95:64]; 
                      3'h3: data_bus = line_temp[127:96]; 
                      3'h4: data_bus = line_temp[159:128];
                      3'h5: data_bus = line_temp[191:160];
                      3'h6: data_bus = line_temp[223:192];
                      3'h7: data_bus = line_temp[255:224];
                    endcase
                  end
                else
                  begin
                    tb1 = xmainmem.xmem1.mem1[addr_bus_me[18:2]];
                    tb2 = xmainmem.xmem1.mem2[addr_bus_me[18:2]];
                    tb3 = xmainmem.xmem1.mem3[addr_bus_me[18:2]];
                    tb4 = xmainmem.xmem1.mem4[addr_bus_me[18:2]];
                    data_bus = {tb4[7:0],tb3[7:0],tb2[7:0],tb1[7:0]};
                  end
		//$save_store();
	      end
	  end
    end

//synopsys translate_on
endmodule