arm9.v

arm10-behavioral的行为仿真代码ｖｅｒｉｌｏｇＨＤＬ

`timescale 1ns/10ps

/*****************************************************************************
$RCSfile: arm9.v,v $
$Revision: 1.47 $
$Author: kohlere $
$Date: 2000/05/04 16:49:02 $
$State: Exp $
$Source: /home/lefurgy/tmp/ISC-repository/isc/hardware/ARM10/behavioral/pipelined/arm9.v,v $

Description: This is a behavioral, 5-stage Pipeline design of an ARM9
		micorprocessor. 

*****************************************************************************/

module arm9 (GCLK, nRESET, ECLK, nFIQ, nIRQ, ISYNC, TESTMODE,
		TESTSELECT, TEST_SI, TEST_SO, MMnWR, MMD, MMA, MCLK,
		DRIVE_MMD_OFFCHIP);

/*------------------------------------------------------------------------
        Ports
------------------------------------------------------------------------*/

input 		GCLK;		//Clock Signal
input 		nRESET;		//Reset Signal
input		nFIQ;		//Fast Interrupt Request (active low)
input		nIRQ;		//Normal Interrupt Request (active low)
input		ISYNC;		//Synchronous nFIQ, nIRQ when low
input		TESTMODE;	//Test Mode Control Signal
input	[1:0]	TESTSELECT;	//Scan Chain Select Logic
input		TEST_SI;	//Scan Chain Input

inout	[31:0]	MMD;		//Main Memory Data Bus
output	[31:0]	MMA;		//Main Memory Address Bus
output		MMnWR;		//Main Memory Not Write, Read
output		MCLK;		//Clock to Memory
output		ECLK;		//External Clock (Clock Driving ARM)
output		TEST_SO;	//Scan Chain Output
output		DRIVE_MMD_OFFCHIP;	//Drive the MMD Bus

/*------------------------------------------------------------------------
        Variable/Signal Declarations
------------------------------------------------------------------------*/
wire	[31:0]	inst_count;

reg     [63:0]  pre_data_bus;  
wire	[31:0]	rf_a;
wire	[31:0]	rf_b;
reg     [31:0]  addr_bus;   
reg     [31:0]  data_bus;   
reg	[1:0]	DMAS;
reg		TEST_SO;

wire    [63:0]  data_bus_me;
wire	[95:0]	ID;
wire	[31:0]	inst_if;
wire	[31:0] 	IA;
wire	[31:0]	imiss_addr;
wire	[31:0]	dmiss_addr;
wire	[31:0]	write_a;
wire	[31:0]	write_b;
wire	[31:0]	pc_if;
wire	[31:0]	ex_result;
wire	[31:0]	store_addr;
reg	[31:0]	addr_bus_me;
wire	[31:0]	me_result;
wire	[31:0]  addr_me;
wire	[31:0]  base_ex;	
wire	[31:0]  base_me;
wire	[31:0]	cop_data_ex;
wire	[31:0]	MMA;
wire	[31:0]	MMD;
wire	[31:0]	count;
wire	[31:0]	cyc_count;
wire	[31:0]	swic_data;
wire	[7:0]	shift_amount_id;
wire	[4:0]	mode;
wire	[4:0]	index_a;
wire	[4:0]	index_b;
wire	[4:0]	Rd_ex;
wire	[4:0]	Rn_ex;
wire	[4:0]	Rd_me;
wire	[4:0]	Rn_me;
wire	[4:0]	w_addr_a;
wire	[4:0]	w_addr_b;
wire    [3:0]   alu_opcode_id;
wire    [3:0]   condition_id; 
wire	[3:0]	inst_type_ex;
wire	[3:0]	inst_type_id;
wire	[3:0]	flags_ex;
wire	[2:0]	shift_type_id;
wire	[6:4]	ir_id;
wire	[1:0]	exc_code;
wire	[1:0]	CHSD, CHSE;
wire		PASS;
wire		LATECANCEL = 1'b0;
wire		IABORT;
wire		DABORT;
wire		nWAIT;
wire		InMREQ;
wire		DnMREQ;
wire		DnWR;
wire		iswic;
wire		dswic;
wire		dwb;
wire		dmiss;
wire		imiss;
wire		doublehold;
wire		stop_me;
wire		fiq_disable;
wire		irq_disable;
wire		rfw_ena_a;
wire		newline;
wire		rfw_ena_b;
wire		second_id;
wire		second_nlu_id;
wire		need_2cycles_id;
wire		load_use_id;		
wire		useMini;
wire		load_pc_ex;
wire		cop_mem_ld;
wire		cop_mem_st;
wire		ldm_id;
wire		stm_id;
wire		mcr_ex;
wire		prediction_stall;
wire		ptaken_ex;
wire		finished_id;
wire		double_id;
wire		double_ex;
wire		double_me;
wire		exception_to_id;
wire		pc_touched;
wire		mispredicted_if;
wire		misp_rec;
wire		s;
wire		mul_first_id;
wire		second_ex;
wire		write_Rd_ex;
wire		write_Rn_ex;
wire		unsigned_byte_ex;
wire		signed_byte_ex;
wire		unsigned_hw_ex;
wire		signed_hw_ex;
wire		write_Rd_me;
wire		dc_init;
wire		ic_init;
wire		write_Rn_me;
wire		write_Rd_wb;
wire		write_Rn_wb;
wire		mem_rd_wr;
wire		mem_ena;
wire		ic_read_mmd;
wire		dc_read_mmd;
wire		drive_mmd;
wire		byte;
wire		halfword;
wire            if_enbar;
wire            id_enbar;
wire            ex_enbar; 
wire            me_enbar;   
wire            wb_enbar;
wire		cop_mem_id;
wire		cop_id;	
wire		cop_absent_int;
wire		pc_mod_ex;
wire		write_Pc_Rn_ex;
wire		write_Pc_Rd_ex;
wire		reset_write_Rd_me;
wire		reset_write_Rn_me;
wire		hold_next_ex;
wire		load_pc_me;
wire		ECLK;
wire            inst_finished;
wire		test_so_cnt;
wire		test_so_id;
wire		test_so_ex;
wire		test_so_me;
wire		MCLK;
wire		istall;
wire		data_decomp;
wire		dflush;	
wire		eval;
wire		pt;
wire		put;
reg		nreset;

/*------------------------------------------------------------------------
        Component Instantiations
------------------------------------------------------------------------*/
//And the CLK to compensate for memory delays
assign ECLK = (!nWAIT | GCLK);

//Latch the reset  signal in case its shorter than one cycle
always @(posedge GCLK or negedge nRESET)
  begin
    if (~nRESET)
      nreset <= 1'b0;
    else if (nWAIT)
      nreset <= nRESET;
  end


always @(double_me or halfword or byte)
  begin
	if (double_me)
	  DMAS = 2'h3;
	else if (halfword)
	  DMAS = 2'h1;
	else if (byte)
	  DMAS = 2'h0;
	else
	  DMAS = 2'h2;
  end

//Create a Clock Tree, sort of
wire eclk_1, eclk1_1, eclk1_2, eclk11_1, eclk11_2,
	eclk12_1, eclk12_2, eclk21_1, eclk111_1, eclk111_2,
	eclk112_1, eclk112_2, eclk121_1, eclk121_2, 
	eclk122_1, eclk122_2,
	eclk1, eclk2, eclk3, eclk4, eclk5, eclk6, eclk7, 
        eclk8, eclk9, eclk10, eclk11, eclk12, eclk13, eclk14,
	eclk15, eclk16, eclk17, eclk18, eclk19, eclk20, eclk21,
	eclk22, eclk23, eclk24, gclk1, gclk2, gclk3, gclk4, gclk5;

/* May End up Using Buffers Here */
nb1s1 	xcb1 	(.Q(eclk_1), .DIN(ECLK));
nb1s2	xcb2	(.Q(eclk1_1), .DIN(eclk_1));
nb1s2	xcb3	(.Q(eclk1_2), .DIN(eclk_1));
nb1s4	xcb4	(.Q(eclk11_1), .DIN(eclk1_1));
nb1s4	xcb5	(.Q(eclk11_2), .DIN(eclk1_1));
nb1s4   xcb6    (.Q(eclk12_1), .DIN(eclk1_2));
nb1s4   xcb7    (.Q(eclk12_2), .DIN(eclk1_2));
nb1s8   xcb8    (.Q(eclk111_1), .DIN(eclk11_1));
nb1s8   xcb9    (.Q(eclk111_2), .DIN(eclk11_1));
nb1s8   xcb10   (.Q(eclk112_1), .DIN(eclk11_2));
nb1s8   xcb11   (.Q(eclk112_2), .DIN(eclk11_2));
nb1s8   xcb12   (.Q(eclk121_1), .DIN(eclk12_1));
nb1s8   xcb13   (.Q(eclk121_2), .DIN(eclk12_1));
nb1s8   xcb14   (.Q(eclk122_1), .DIN(eclk12_2));
nb1s8   xcb15   (.Q(eclk122_2), .DIN(eclk12_2));
ib1s12   xcb16   (.Q(eclk1), .DIN(eclk111_1));
ib1s12   xcb17   (.Q(eclk2), .DIN(eclk111_1));
ib1s12   xcb18   (.Q(eclk3), .DIN(eclk111_1));
ib1s12   xcb19   (.Q(eclk4), .DIN(eclk111_2));
ib1s12   xcb20   (.Q(eclk5), .DIN(eclk111_2));
ib1s12   xcb21   (.Q(eclk6), .DIN(eclk111_2));
ib1s12   xcb22   (.Q(eclk7), .DIN(eclk112_1));
ib1s12   xcb23   (.Q(eclk8), .DIN(eclk112_1));
ib1s12   xcb24   (.Q(eclk9), .DIN(eclk112_1));
ib1s12   xcb25   (.Q(eclk10), .DIN(eclk112_2));
ib1s12   xcb26   (.Q(eclk11), .DIN(eclk112_2));
ib1s12   xcb27   (.Q(eclk12), .DIN(eclk112_2));
ib1s12   xcb28   (.Q(eclk13), .DIN(eclk121_1));
ib1s12   xcb29   (.Q(eclk14), .DIN(eclk121_1));
ib1s12   xcb30   (.Q(eclk15), .DIN(eclk121_1));
ib1s12   xcb31   (.Q(eclk16), .DIN(eclk121_2));
ib1s12   xcb32   (.Q(eclk17), .DIN(eclk121_2));
ib1s12   xcb33   (.Q(eclk18), .DIN(eclk121_2));
ib1s12   xcb34   (.Q(eclk19), .DIN(eclk122_1));
ib1s12   xcb35   (.Q(eclk20), .DIN(eclk122_1));
ib1s12   xcb36   (.Q(eclk21), .DIN(eclk122_1));
ib1s12   xcb37   (.Q(eclk22), .DIN(eclk122_2));
ib1s12   xcb38   (.Q(eclk23), .DIN(eclk122_2));
ib1s12   xcb39   (.Q(eclk24), .DIN(eclk122_2));

nb1s1	xcb40	(.Q(gclk1), .DIN(GCLK));
nb1s2	xcb41	(.Q(gclk2), .DIN(gclk1));
nb1s4   xcb42	(.Q(gclk3), .DIN(gclk2));
nb1s8	xcb43	(.Q(gclk4), .DIN(gclk3));
ib1s12	xcb44	(.Q(gclk5), .DIN(gclk4));
assign MCLK = ~gclk3;

/* Need Logic to Select the Hook-up the Proper Scan Chains; */
reg test_cnt, test_id, test_ex, test_me;
always @(TESTSELECT or TEST_SI or test_so_cnt or test_so_id or
	  test_so_ex or test_so_me)
  begin
    case (TESTSELECT)
      2'h0: begin 
	      test_cnt <= TEST_SI;
	      test_id <= 1'b0;
              test_ex <= 1'b0;
              test_me <= 1'b0;
              TEST_SO <= test_so_cnt;
            end
      2'h1: begin
              test_cnt <= 1'b0;
              test_id <= TEST_SI;
              test_ex <= 1'b0;
              test_me <= 1'b0;
	      TEST_SO <= test_so_id;
            end
      2'h2: begin
              test_cnt <= 1'b0;
              test_id <= 1'b0;
              test_ex <= TEST_SI;
              test_me <= 1'b0;
	      TEST_SO <= test_so_ex;
            end
      2'h3: begin
              test_cnt <= 1'b0;
              test_id <= 1'b0;
              test_ex <= 1'b0;
              test_me <= TEST_SI;
	      TEST_SO <= test_so_me;
            end
    endcase
  end

control xcontrol (.nGCLK1_if(eclk2), .nGCLK2_if(eclk3), .nGCLK3_if(eclk4),
//		.test_se(TESTMODE), .test_si(test_cnt), .test_so(test_so_cnt),
		.nGCLK_int(eclk1), .if_enbar(if_enbar),
		.TESTMODE(TESTMODE), .nRESET(nRESET), .DABORT(DABORT),
		.IABORT(IABORT), .nFIQ(nFIQ), .nIRQ(nIRQ),
                .ISYNC(ISYNC), .CHSD(CHSD), .CHSE(CHSE), .ID(ID), .IA(IA),
		.irq_disable(irq_disable), .fiq_disable(fiq_disable),
                .flags_ex(flags_ex), .load_pc_me(load_pc_me),
		.exception_to_id(exception_to_id), .pc_touched(pc_touched),
		.pc(pc_if), .inst_if(inst_if), .misp_rec(misp_rec),
                .mispredicted_if(mispredicted_if), .me_result(me_result),
		.base_me(base_me), .ex_result(ex_result),
                .Rd_ex(Rd_ex), .Rd_me(Rd_me), .InMREQ(InMREQ),
		.Rn_me(Rn_me), .hold_next_ex(hold_next_ex), 
                .load_pc_ex(load_pc_ex), .exc_code(exc_code),
		.newline(newline), .Rn_ex(Rn_ex), .ptaken_ex(ptaken_ex),
		.need_2cycles_id(need_2cycles_id), .pt(pt), .put(put),
                .second_id(second_id), .load_use_id(load_use_id),
		.ldm_id(ldm_id), .stm_id(stm_id),
		.finished_id(finished_id), .id_enbar(id_enbar),
		.ex_enbar(ex_enbar), .pc_mod_ex(pc_mod_ex),
		.me_enbar(me_enbar), .wb_enbar(wb_enbar), .cop_id(cop_id),
                .cop_absent_int(cop_absent_int),
		.write_Pc_Rn_ex(write_Pc_Rn_ex),
		.write_Pc_Rd_ex(write_Pc_Rd_ex), .eval(eval),
                .reset_write_Rn_me(reset_write_Rn_me),
		.reset_write_Rd_me(reset_write_Rd_me));

/* Comment out first two for non-structural code. */
pipe	xpipe	(
//		.test_si1(test_si_me), .test_si2(test_si_id),
//              .test_si3(test_si_ex), .test_se(TESTMODE),
		.test_so_ex(test_so_ex), .test_so_me(test_so_me),
		.test_so_id(test_so_id),
		.nGCLK_id(eclk1), .nGCLK1_ex(eclk16), .nGCLK2_ex(eclk17),
		.nGCLK3_ex(eclk18), .nGCLK_me(eclk13), .TESTMODE(TESTMODE),
                .nRESET(nRESET), .id_enbar(id_enbar), .ex_enbar(ex_enbar),
		.me_enbar(me_enbar), .inst_if(inst_if), .rf_a(rf_a),
		.rf_b(rf_b), .index_a(index_a), .index_b(index_b),
		.finished_id(finished_id), .second_id(second_id),
		.need_2cycles_id(need_2cycles_id), .exception_to_id(exception_to_id),
		.exc_code(exc_code), .hold_next_ex(hold_next_ex),
		.write_Pc_Rn_ex(write_Pc_Rn_ex), .DnWR(DnWR),
		.write_Pc_Rd_ex(write_Pc_Rd_ex), .DnMREQ(DnMREQ),
		.PASS(PASS), .ldm_id(ldm_id), .stm_id(stm_id),
		.load_use_id(load_use_id), .cop_id(cop_id),
		.pc_mod_ex(pc_mod_ex), .Rn_ex(Rn_ex), .Rd_ex(Rd_ex),
		.load_pc_ex(load_pc_ex), .store_addr(store_addr),
                .ex_result(ex_result), .stop_me(stop_me),
		.flags_ex(flags_ex), .Rn_me(Rn_me), .Rd_me(Rd_me), 
		.base_me(base_me), .me_result(me_result),
		.write_Rd_ex(write_Rd_ex), .load_pc_me(load_pc_me), 
		.data_bus(data_bus_me), .mode(mode),
		.reset_write_Rd_me(reset_write_Rd_me),
		.reset_write_Rn_me(reset_write_Rn_me),
		.double_me(double_me), .byte_me(byte),
		.halfword_me(halfword), .store_ex(store_ex),
		.pc_if(pc_if), .cop_absent_int(cop_absent_int),
                .mispredicted_if(mispredicted_if),
		.irq_disable(irq_disable),
		.fiq_disable(fiq_disable), .BIGEND(BIGEND),
		.write_Rd_me(write_Rd_me), .write_Rn_me(write_Rn_me));

wire wena_a = write_Rd_me & ~wb_enbar;
wire wena_b = write_Rn_me & ~wb_enbar;

//Comment Out First Line for Checker 
regfile xrf	(.nRESET(nRESET),
//regfile xrf	(.nRESET(1'b1),
		.nGCLK1(eclk5), .nGCLK2(eclk6), .nGCLK3(eclk7),
		.nGCLK4(eclk8), .nGCLK5(eclk9), .nGCLK6(eclk10), 
                .nGCLK7(eclk11), .nGCLK8(eclk12), .pc_if(pc_if),
		.index_a(index_a), .index_b(index_b), 
		.write_a(me_result), .write_b(base_me),
		.wena_a(wena_a), .wena_b(wena_b), .w_addr_a(Rd_me),
		.w_addr_b(Rn_me), .port_a(rf_a), .port_b(rf_b));

mmu	xmmu 	(.nECLK1(eclk19), .nECLK2(eclk20), .nECLK3(eclk21),
		.nECLK4(eclk22), .nECLK5(eclk23), .nECLK6(eclk24), 
		.nRESET(nRESET), .nWAIT(nWAIT), .CHSD(CHSD), .CHSE(CHSE),
		.id_enbar(id_enbar), .BIGEND(BIGEND), .inst_if(inst_if),
		.LATECANCEL(LATECANCEL), .PASS(PASS), .IABORT(IABORT),
		.DABORT(DABORT), .MMA(MMA), .MMnWR(MMnWR),
		.nGCLK(gclk5), .dwb(dwb), .drive_mmd(drive_mmd),
		.ex_enbar(ex_enbar), .imiss(imiss), .dmiss(dmiss),
		.imiss_addr(imiss_addr), .dmiss_addr(dmiss_addr),
		.ic_read_mmd(ic_read_mmd), .dc_read_mmd(dc_read_mmd),
		.DD(data_bus_me), .doublehold(doublehold), .IA(IA),
		.InMREQ(InMREQ), .useMini(useMini), .iswic(iswic),
		.swic_data(swic_data), .dswic(dswic), .dflush(dflush),
		.dc_init(dc_init), .ic_init(ic_init), .istall(istall),
		.DA(store_addr), .DnMREQ(DnMREQ), .mode(mode),
		.me_enbar(me_enbar), .data_decomp(data_decomp),
		.mispredicted(mispredicted_if), .misp_rec(misp_rec),
		.pc_touched(pc_touched), .hold_next_ex(hold_next_ex),
		.ptaken_ex(ptaken_ex), .pt(pt), .put(put), .eval(eval),
		.inst_count(inst_count), .inst_finished(inst_finished),
		.if_enbar(if_enbar), .stop_me(stop_me));

reg DRIVE_MMD_OFFCHIP;
always @(posedge gclk5 or negedge nRESET)
  begin
    if (~nRESET)
      DRIVE_MMD_OFFCHIP <= #1 1'b0;
    else