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arm10-behavioral的行为仿真代码ｖｅｒｉｌｏｇＨＤＬ

This directory contains the behavioral model of the ARM pipeline and its
associated cache controllers, memory modules, and test bench.  The
behavioral code has been augmented with certain structural components 
for creating a clock tree and preventing data from streaming through
pipeline latches due to clock skew.  When timing driven routing can
be used, this logic can be stripped from the design.  

File 		Description:
==================================================================
./fpga2		Directory containing Xilinx FPGA Implementation
Makefile	Makefile for setting up the Checker
DW01_decode.v	Synopsys DesignWare Decoder
align.v		Data Aligner for Byte/Halfword/Word Access
alu.v		ALU
arm9.m		VerilogXL simulation master file
arm9.v		ARM Processor Top Level Module
comp42_2.v	4-2 Compressor used in Multiplier
comp42_n40.v	Level 0 Bank of Compressors (40 of comp42_2)
comp42_n64.v	Level 1 Bank of Compressors (64 of comp42_2)
control.v	Instantiates the ifetch, interlock, and counters blocks
dcache.v	Data Cache Controller
ex.v		Execute Stage of Pipeline
fxu_pli_utils.* Used with Checker
icache.v	Instruction Cache Controller
id.v		Instruction Decode Stage of Pipeline
idt71v546s100.v ZBT SRAM model
ifetch.v	Instruction Fetch and Branch Prediciton Unit
interlock.v	Stall Controller
lec25dscc25.v	LEDA Library for synthesis
lec25ioscp25.v  LEDA I/O Library for synthesis
mainmem.v	Instantiates the SRAM 
mapreg.v	Maps Register Indexes by Mode
mapspsr.v	Maps SPSR Indexes by Mode
me.v		Memory Stage of PIpeline
miniram.v	Lock Down Cache used for Decompression
mmu.v		Memory Management Unit and Decompression Controller
mult.v		Multiplier top-level module
multacc.v	32x8 multiplier
pardef.*	Parameters and Define Statements
pipe.v		Instantiates the Execute, Decode, and Memory Stages
ppselect.v	Partial Product Select for Booth Recoding
ram.v		RAM model for caches
regfile.v	Register File
setup.do	SignalScan Startup file
shifter.v	Shift Unit
simcon.v	Used for Checker
tag.v		TAG model for caches
testarm.m	VCS Masterfile
testarm.s	Test Program (ARM Code)
testarm.v	Test Bench
testarm.vhx	Disassembled Test Program (Memory File)
wb.v		Write Back Pipeline Stage (Unused)

/*************************************************************************
Below is the ARM heirarchy
*************************************************************************/

testarm.v
  arm9.v
     regfile.v
     mmu.v 
     icache.v
        ram.v
        tag.v 
        miniram.v  
     dcache.v
        ram.v 
        tag.v   
     mainmem.v
        idt71v546s100.v
     control.v
        ifetch.v
        interlock.v
        counters.v
     pipe.v
        me.v
           align.v
        id.v
           mapreg.v
           decode.v
        ex.v
           alu.v
           shifter.v
           mapspsr.v
           mult.v
              multacc.v
                 ppselect.v
                 comp42_n40.v
                    comp42_2.v
                 comp42_n64.v
                    comp42_2.v