sec_clock.tan.summary

来自「基于CYCLONE系列FPGA EP1C3T144C8的VHDL秒表代码」· SUMMARY 代码 · 共 57 行

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Timing Analyzer Summary
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Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 21.800 ns
From           : led_6[2]
To             : data[0]
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 160.59 MHz ( period = 6.227 ns )
From           : led_6[1]
To             : led_2[2]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'start'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 275.03 MHz ( period = 3.636 ns )
From           : start1
To             : start1
From Clock     : start
To Clock       : start
Failed Paths   : 0

Type           : Clock Setup: 'rst'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 275.03 MHz ( period = 3.636 ns )
From           : rst1
To             : rst1
From Clock     : rst
To Clock       : rst
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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