📄 prev_cmp_sec_clock.qmsg
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{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Oct 08 20:18:48 2008 " "Info: Processing started: Wed Oct 08 20:18:48 2008" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off sec_clock -c sec_clock " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off sec_clock -c sec_clock" { } { } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "127 " "Info: Allocated 127 megabytes of memory during processing" { } { } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Oct 08 20:18:49 2008 " "Info: Processing ended: Wed Oct 08 20:18:49 2008" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Oct 08 20:18:50 2008 " "Info: Processing started: Wed Oct 08 20:18:50 2008" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off sec_clock -c sec_clock --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off sec_clock -c sec_clock --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" { } { { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 4 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "rst " "Info: Assuming node \"rst\" is an undefined clock" { } { { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 5 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "rst" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "start " "Info: Assuming node \"start\" is an undefined clock" { } { { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 6 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "start" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clk1 " "Info: Detected ripple clock \"clk1\" as buffer" { } { { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 11 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk1" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} } { } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register num\[0\] register num\[16\] 166.42 MHz 6.009 ns Internal " "Info: Clock \"clk\" has Internal fmax of 166.42 MHz between source register \"num\[0\]\" and destination register \"num\[16\]\" (period= 6.009 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.748 ns + Longest register register " "Info: + Longest register to register delay is 5.748 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns num\[0\] 1 REG LC_X8_Y5_N1 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y5_N1; Fanout = 4; REG Node = 'num\[0\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { num[0] } "NODE_NAME" } } { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 29 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.542 ns) + CELL(0.590 ns) 1.132 ns LessThan0~280 2 COMB LC_X8_Y5_N0 1 " "Info: 2: + IC(0.542 ns) + CELL(0.590 ns) = 1.132 ns; Loc. = LC_X8_Y5_N0; Fanout = 1; COMB Node = 'LessThan0~280'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.132 ns" { num[0] LessThan0~280 } "NODE_NAME" } } { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.099 ns) + CELL(0.114 ns) 2.345 ns LessThan0~281 3 COMB LC_X7_Y5_N2 1 " "Info: 3: + IC(1.099 ns) + CELL(0.114 ns) = 2.345 ns; Loc. = LC_X7_Y5_N2; Fanout = 1; COMB Node = 'LessThan0~281'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.213 ns" { LessThan0~280 LessThan0~281 } "NODE_NAME" } } { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 2.641 ns LessThan0~282 4 COMB LC_X7_Y5_N3 1 " "Info: 4: + IC(0.182 ns) + CELL(0.114 ns) = 2.641 ns; Loc. = LC_X7_Y5_N3; Fanout = 1; COMB Node = 'LessThan0~282'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.296 ns" { LessThan0~281 LessThan0~282 } "NODE_NAME" } } { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 2.937 ns LessThan0~283 5 COMB LC_X7_Y5_N4 1 " "Info: 5: + IC(0.182 ns) + CELL(0.114 ns) = 2.937 ns; Loc. = LC_X7_Y5_N4; Fanout = 1; COMB Node = 'LessThan0~283'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.296 ns" { LessThan0~282 LessThan0~283 } "NODE_NAME" } } { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.340 ns) + CELL(0.114 ns) 3.391 ns LessThan0~285 6 COMB LC_X7_Y5_N5 20 " "Info: 6: + IC(0.340 ns) + CELL(0.114 ns) = 3.391 ns; Loc. = LC_X7_Y5_N5; Fanout = 20; COMB Node = 'LessThan0~285'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.454 ns" { LessThan0~283 LessThan0~285 } "NODE_NAME" } } { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.245 ns) + CELL(1.112 ns) 5.748 ns num\[16\] 7 REG LC_X8_Y4_N7 4 " "Info: 7: + IC(1.245 ns) + CELL(1.112 ns) = 5.748 ns; Loc. = LC_X8_Y4_N7; Fanout = 4; REG Node = 'num\[16\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.357 ns" { LessThan0~285 num[16] } "NODE_NAME" } } { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 29 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.158 ns ( 37.54 % ) " "Info: Total cell delay = 2.158 ns ( 37.54 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.590 ns ( 62.46 % ) " "Info: Total interconnect delay = 3.590 ns ( 62.46 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.748 ns" { num[0] LessThan0~280 LessThan0~281 LessThan0~282 LessThan0~283 LessThan0~285 num[16] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.748 ns" { num[0] {} LessThan0~280 {} LessThan0~281 {} LessThan0~282 {} LessThan0~283 {} LessThan0~285 {} num[16] {} } { 0.000ns 0.542ns 1.099ns 0.182ns 0.182ns 0.340ns 1.245ns } { 0.000ns 0.590ns 0.114ns 0.114ns 0.114ns 0.114ns 1.112ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.730 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.730 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_93 34 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 34; CLK Node = 'clk'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 4 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.711 ns) 2.730 ns num\[16\] 2 REG LC_X8_Y4_N7 4 " "Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X8_Y4_N7; Fanout = 4; REG Node = 'num\[16\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.261 ns" { clk num[16] } "NODE_NAME" } } { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 29 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.85 % ) " "Info: Total cell delay = 2.180 ns ( 79.85 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.550 ns ( 20.15 % ) " "Info: Total interconnect delay = 0.550 ns ( 20.15 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.730 ns" { clk num[16] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.730 ns" { clk {} clk~out0 {} num[16] {} } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.730 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.730 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_93 34 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 34; CLK Node = 'clk'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 4 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.711 ns) 2.730 ns num\[0\] 2 REG LC_X8_Y5_N1 4 " "Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X8_Y5_N1; Fanout = 4; REG Node = 'num\[0\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.261 ns" { clk num[0] } "NODE_NAME" } } { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 29 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.85 % ) " "Info: Total cell delay = 2.180 ns ( 79.85 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.550 ns ( 20.15 % ) " "Info: Total interconnect delay = 0.550 ns ( 20.15 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.730 ns" { clk num[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.730 ns" { clk {} clk~out0 {} num[0] {} } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.730 ns" { clk num[16] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.730 ns" { clk {} clk~out0 {} num[16] {} } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.730 ns" { clk num[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.730 ns" { clk {} clk~out0 {} num[0] {} } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" { } { { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 29 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 29 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.748 ns" { num[0] LessThan0~280 LessThan0~281 LessThan0~282 LessThan0~283 LessThan0~285 num[16] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.748 ns" { num[0] {} LessThan0~280 {} LessThan0~281 {} LessThan0~282 {} LessThan0~283 {} LessThan0~285 {} num[16] {} } { 0.000ns 0.542ns 1.099ns 0.182ns 0.182ns 0.340ns 1.245ns } { 0.000ns 0.590ns 0.114ns 0.114ns 0.114ns 0.114ns 1.112ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.730 ns" { clk num[16] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.730 ns" { clk {} clk~out0 {} num[16] {} } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.730 ns" { clk num[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.730 ns" { clk {} clk~out0 {} num[0] {} } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "rst register register rst1 rst1 275.03 MHz Internal " "Info: Clock \"rst\" Internal fmax is restricted to 275.03 MHz between source register \"rst1\" and destination register \"rst1\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.823 ns + Longest register register " "Info: + Longest register to register delay is 0.823 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns rst1 1 REG LC_X26_Y2_N3 33 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X26_Y2_N3; Fanout = 33; REG Node = 'rst1'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { rst1 } "NODE_NAME" } } { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 24 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.514 ns) + CELL(0.309 ns) 0.823 ns rst1 2 REG LC_X26_Y2_N3 33 " "Info: 2: + IC(0.514 ns) + CELL(0.309 ns) = 0.823 ns; Loc. = LC_X26_Y2_N3; Fanout = 33; REG Node = 'rst1'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.823 ns" { rst1 rst1 } "NODE_NAME" } } { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 24 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.309 ns ( 37.55 % ) " "Info: Total cell delay = 0.309 ns ( 37.55 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.514 ns ( 62.45 % ) " "Info: Total interconnect delay = 0.514 ns ( 62.45 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.823 ns" { rst1 rst1 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "0.823 ns" { rst1 {} rst1 {} } { 0.000ns 0.514ns } { 0.000ns 0.309ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "rst destination 2.999 ns + Shortest register " "Info: + Shortest clock path from clock \"rst\" to destination register is 2.999 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns rst 1 CLK PIN_76 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_76; Fanout = 1; CLK Node = 'rst'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { rst } "NODE_NAME" } } { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.819 ns) + CELL(0.711 ns) 2.999 ns rst1 2 REG LC_X26_Y2_N3 33 " "Info: 2: + IC(0.819 ns) + CELL(0.711 ns) = 2.999 ns; Loc. = LC_X26_Y2_N3; Fanout = 33; REG Node = 'rst1'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.530 ns" { rst rst1 } "NODE_NAME" } } { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 24 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 72.69 % ) " "Info: Total cell delay = 2.180 ns ( 72.69 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.819 ns ( 27.31 % ) " "Info: Total interconnect delay = 0.819 ns ( 27.31 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.999 ns" { rst rst1 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.999 ns" { rst {} rst~out0 {} rst1 {} } { 0.000ns 0.000ns 0.819ns } { 0.000ns 1.469ns 0.711ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "rst source 2.999 ns - Longest register " "Info: - Longest clock path from clock \"rst\" to source register is 2.999 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns rst 1 CLK PIN_76 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_76; Fanout = 1; CLK Node = 'rst'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { rst } "NODE_NAME" } } { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.819 ns) + CELL(0.711 ns) 2.999 ns rst1 2 REG LC_X26_Y2_N3 33 " "Info: 2: + IC(0.819 ns) + CELL(0.711 ns) = 2.999 ns; Loc. = LC_X26_Y2_N3; Fanout = 33; REG Node = 'rst1'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.530 ns" { rst rst1 } "NODE_NAME" } } { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 24 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 72.69 % ) " "Info: Total cell delay = 2.180 ns ( 72.69 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.819 ns ( 27.31 % ) " "Info: Total interconnect delay = 0.819 ns ( 27.31 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.999 ns" { rst rst1 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.999 ns" { rst {} rst~out0 {} rst1 {} } { 0.000ns 0.000ns 0.819ns } { 0.000ns 1.469ns 0.711ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.999 ns" { rst rst1 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.999 ns" { rst {} rst~out0 {} rst1 {} } { 0.000ns 0.000ns 0.819ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.999 ns" { rst rst1 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.999 ns" { rst {} rst~out0 {} rst1 {} } { 0.000ns 0.000ns 0.819ns } { 0.000ns 1.469ns 0.711ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" { } { { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 24 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 24 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.823 ns" { rst1 rst1 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "0.823 ns" { rst1 {} rst1 {} } { 0.000ns 0.514ns } { 0.000ns 0.309ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.999 ns" { rst rst1 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.999 ns" { rst {} rst~out0 {} rst1 {} } { 0.000ns 0.000ns 0.819ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.999 ns" { rst rst1 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.999 ns" { rst {} rst~out0 {} rst1 {} } { 0.000ns 0.000ns 0.819ns } { 0.000ns 1.469ns 0.711ns } "" } } } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { rst1 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { rst1 {} } { } { } "" } } { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 24 -1 0 } } } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "start register register start1 start1 275.03 MHz Internal " "Info: Clock \"start\" Internal fmax is restricted to 275.03 MHz between source register \"start1\" and destination register \"start1\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.846 ns + Longest register register " "Info: + Longest register to register delay is 0.846 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns start1 1 REG LC_X18_Y9_N6 19 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X18_Y9_N6; Fanout = 19; REG Node = 'start1'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { start1 } "NODE_NAME" } } { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 23 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.537 ns) + CELL(0.309 ns) 0.846 ns start1 2 REG LC_X18_Y9_N6 19 " "Info: 2: + IC(0.537 ns) + CELL(0.309 ns) = 0.846 ns; Loc. = LC_X18_Y9_N6; Fanout = 19; REG Node = 'start1'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.846 ns" { start1 start1 } "NODE_NAME" } } { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 23 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.309 ns ( 36.52 % ) " "Info: Total cell delay = 0.309 ns ( 36.52 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.537 ns ( 63.48 % ) " "Info: Total interconnect delay = 0.537 ns ( 63.48 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.846 ns" { start1 start1 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "0.846 ns" { start1 {} start1 {} } { 0.000ns 0.537ns } { 0.000ns 0.309ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "start destination 4.196 ns + Shortest register " "Info: + Shortest clock path from clock \"start\" to destination register is 4.196 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns start 1 CLK PIN_91 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_91; Fanout = 1; CLK Node = 'start'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { start } "NODE_NAME" } } { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.016 ns) + CELL(0.711 ns) 4.196 ns start1 2 REG LC_X18_Y9_N6 19 " "Info: 2: + IC(2.016 ns) + CELL(0.711 ns) = 4.196 ns; Loc. = LC_X18_Y9_N6; Fanout = 19; REG Node = 'start1'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.727 ns" { start start1 } "NODE_NAME" } } { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 23 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 51.95 % ) " "Info: Total cell delay = 2.180 ns ( 51.95 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.016 ns ( 48.05 % ) " "Info: Total interconnect delay = 2.016 ns ( 48.05 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.196 ns" { start start1 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.196 ns" { start {} start~out0 {} start1 {} } { 0.000ns 0.000ns 2.016ns } { 0.000ns 1.469ns 0.711ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "start source 4.196 ns - Longest register " "Info: - Longest clock path from clock \"start\" to source register is 4.196 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns start 1 CLK PIN_91 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_91; Fanout = 1; CLK Node = 'start'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { start } "NODE_NAME" } } { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.016 ns) + CELL(0.711 ns) 4.196 ns start1 2 REG LC_X18_Y9_N6 19 " "Info: 2: + IC(2.016 ns) + CELL(0.711 ns) = 4.196 ns; Loc. = LC_X18_Y9_N6; Fanout = 19; REG Node = 'start1'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.727 ns" { start start1 } "NODE_NAME" } } { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 23 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 51.95 % ) " "Info: Total cell delay = 2.180 ns ( 51.95 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.016 ns ( 48.05 % ) " "Info: Total interconnect delay = 2.016 ns ( 48.05 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.196 ns" { start start1 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.196 ns" { start {} start~out0 {} start1 {} } { 0.000ns 0.000ns 2.016ns } { 0.000ns 1.469ns 0.711ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.196 ns" { start start1 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.196 ns" { start {} start~out0 {} start1 {} } { 0.000ns 0.000ns 2.016ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.196 ns" { start start1 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.196 ns" { start {} start~out0 {} start1 {} } { 0.000ns 0.000ns 2.016ns } { 0.000ns 1.469ns 0.711ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" { } { { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 23 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 23 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.846 ns" { start1 start1 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "0.846 ns" { start1 {} start1 {} } { 0.000ns 0.537ns } { 0.000ns 0.309ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.196 ns" { start start1 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.196 ns" { start {} start~out0 {} start1 {} } { 0.000ns 0.000ns 2.016ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.196 ns" { start start1 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.196 ns" { start {} start~out0 {} start1 {} } { 0.000ns 0.000ns 2.016ns } { 0.000ns 1.469ns 0.711ns } "" } } } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { start1 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { start1 {} } { } { } "" } } { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 23 -1 0 } } } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk data\[0\] led_2\[0\] 22.009 ns register " "Info: tco from clock \"clk\" to destination pin \"data\[0\]\" through register \"led_2\[0\]\" is 22.009 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.682 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 7.682 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_93 34 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 34; CLK Node = 'clk'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 4 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.935 ns) 2.954 ns clk1 2 REG LC_X7_Y5_N6 33 " "Info: 2: + IC(0.550 ns) + CELL(0.935 ns) = 2.954 ns; Loc. = LC_X7_Y5_N6; Fanout = 33; REG Node = 'clk1'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.485 ns" { clk clk1 } "NODE_NAME" } } { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.017 ns) + CELL(0.711 ns) 7.682 ns led_2\[0\] 3 REG LC_X19_Y9_N2 5 " "Info: 3: + IC(4.017 ns) + CELL(0.711 ns) = 7.682 ns; Loc. = LC_X19_Y9_N2; Fanout = 5; REG Node = 'led_2\[0\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.728 ns" { clk1 led_2[0] } "NODE_NAME" } } { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 60 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 40.55 % ) " "Info: Total cell delay = 3.115 ns ( 40.55 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.567 ns ( 59.45 % ) " "Info: Total interconnect delay = 4.567 ns ( 59.45 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.682 ns" { clk clk1 led_2[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.682 ns" { clk {} clk~out0 {} clk1 {} led_2[0] {} } { 0.000ns 0.000ns 0.550ns 4.017ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" { } { { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 60 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "14.103 ns + Longest register pin " "Info: + Longest register to pin delay is 14.103 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns led_2\[0\] 1 REG LC_X19_Y9_N2 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X19_Y9_N2; Fanout = 5; REG Node = 'led_2\[0\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { led_2[0] } "NODE_NAME" } } { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 60 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.164 ns) + CELL(0.442 ns) 1.606 ns seg\[0\]~255 2 COMB LC_X19_Y9_N1 1 " "Info: 2: + IC(1.164 ns) + CELL(0.442 ns) = 1.606 ns; Loc. = LC_X19_Y9_N1; Fanout = 1; COMB Node = 'seg\[0\]~255'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.606 ns" { led_2[0] seg[0]~255 } "NODE_NAME" } } { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.247 ns) + CELL(0.292 ns) 3.145 ns seg\[0\]~256 3 COMB LC_X19_Y10_N8 1 " "Info: 3: + IC(1.247 ns) + CELL(0.292 ns) = 3.145 ns; Loc. = LC_X19_Y10_N8; Fanout = 1; COMB Node = 'seg\[0\]~256'" { } { { "d:/altera/72/quartus/bin/TimingClosureFlo⌨️ 快捷键说明
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