prev_cmp_sec_clock.qmsg

基于CYCLONE系列FPGA EP1C3T144C8的VHDL秒表代码

{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0 0 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" 1 0 "" 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0 0 "Finished moving registers into I/O cells, LUTs, and RAM blocks" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" {  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "5.817 ns register register " "Info: Estimated most critical path is register to register delay of 5.817 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns num\[3\] 1 REG LAB_X8_Y5 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X8_Y5; Fanout = 3; REG Node = 'num\[3\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { num[3] } "NODE_NAME" } } { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.616 ns) + CELL(0.114 ns) 0.730 ns LessThan0~280 2 COMB LAB_X8_Y5 1 " "Info: 2: + IC(0.616 ns) + CELL(0.114 ns) = 0.730 ns; Loc. = LAB_X8_Y5; Fanout = 1; COMB Node = 'LessThan0~280'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.730 ns" { num[3] LessThan0~280 } "NODE_NAME" } } { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.303 ns) + CELL(0.590 ns) 1.623 ns LessThan0~281 3 COMB LAB_X7_Y5 1 " "Info: 3: + IC(0.303 ns) + CELL(0.590 ns) = 1.623 ns; Loc. = LAB_X7_Y5; Fanout = 1; COMB Node = 'LessThan0~281'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.893 ns" { LessThan0~280 LessThan0~281 } "NODE_NAME" } } { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.064 ns) + CELL(0.590 ns) 2.277 ns LessThan0~282 4 COMB LAB_X7_Y5 1 " "Info: 4: + IC(0.064 ns) + CELL(0.590 ns) = 2.277 ns; Loc. = LAB_X7_Y5; Fanout = 1; COMB Node = 'LessThan0~282'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.654 ns" { LessThan0~281 LessThan0~282 } "NODE_NAME" } } { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.064 ns) + CELL(0.590 ns) 2.931 ns LessThan0~283 5 COMB LAB_X7_Y5 1 " "Info: 5: + IC(0.064 ns) + CELL(0.590 ns) = 2.931 ns; Loc. = LAB_X7_Y5; Fanout = 1; COMB Node = 'LessThan0~283'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.654 ns" { LessThan0~282 LessThan0~283 } "NODE_NAME" } } { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.212 ns) + CELL(0.442 ns) 3.585 ns LessThan0~285 6 COMB LAB_X7_Y5 20 " "Info: 6: + IC(0.212 ns) + CELL(0.442 ns) = 3.585 ns; Loc. = LAB_X7_Y5; Fanout = 20; COMB Node = 'LessThan0~285'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.654 ns" { LessThan0~283 LessThan0~285 } "NODE_NAME" } } { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.120 ns) + CELL(1.112 ns) 5.817 ns num\[16\] 7 REG LAB_X8_Y4 4 " "Info: 7: + IC(1.120 ns) + CELL(1.112 ns) = 5.817 ns; Loc. = LAB_X8_Y4; Fanout = 4; REG Node = 'num\[16\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.232 ns" { LessThan0~285 num[16] } "NODE_NAME" } } { "sec_clock.vhd" "" { Text "D:/MY_FILES/sec_clock/sec_clock.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.438 ns ( 59.10 % ) " "Info: Total cell delay = 3.438 ns ( 59.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.379 ns ( 40.90 % ) " "Info: Total interconnect delay = 2.379 ns ( 40.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.817 ns" { num[3] LessThan0~280 LessThan0~281 LessThan0~282 LessThan0~283 LessThan0~285 num[16] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0}