📄 sec_clock_vhd.sdo

📁 基于CYCLONE系列FPGA EP1C3T144C8的VHDL秒表代码
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    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE rst1.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datad (514:514:514) (514:514:514))
        (IOPATH datad regin (309:309:309) (309:309:309))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE rst1.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (1530:1530:1530) (1530:1530:1530))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE start1.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datad (534:534:534) (534:534:534))
        (IOPATH datad regin (309:309:309) (309:309:309))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE start1.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (2618:2618:2618) (2618:2618:2618))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\led_8\[0\]\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datac (536:536:536) (536:536:536))
        (IOPATH datac regin (478:478:478) (478:478:478))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\led_8\[0\]\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (5058:5058:5058) (5058:5058:5058))
        (PORT clk (4721:4721:4721) (4721:4721:4721))
        (PORT ena (2172:2172:2172) (2172:2172:2172))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP ena (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD ena (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\led_8\[3\]\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (571:571:571) (571:571:571))
        (PORT datab (543:543:543) (543:543:543))
        (PORT datac (1216:1216:1216) (1216:1216:1216))
        (PORT datad (778:778:778) (778:778:778))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH datab regin (607:607:607) (607:607:607))
        (IOPATH datac regin (478:478:478) (478:478:478))
        (IOPATH datad regin (309:309:309) (309:309:309))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\led_8\[3\]\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (5058:5058:5058) (5058:5058:5058))
        (PORT clk (4721:4721:4721) (4721:4721:4721))
        (PORT ena (1720:1720:1720) (1720:1720:1720))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP ena (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD ena (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\led_8\[1\]\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (571:571:571) (571:571:571))
        (PORT datab (543:543:543) (543:543:543))
        (PORT datac (1216:1216:1216) (1216:1216:1216))
        (PORT datad (777:777:777) (777:777:777))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH datab regin (607:607:607) (607:607:607))
        (IOPATH datac regin (478:478:478) (478:478:478))
        (IOPATH datad regin (309:309:309) (309:309:309))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\led_8\[1\]\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (5058:5058:5058) (5058:5058:5058))
        (PORT clk (4721:4721:4721) (4721:4721:4721))
        (PORT ena (1720:1720:1720) (1720:1720:1720))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP ena (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD ena (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\led_8\[2\]\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1213:1213:1213) (1213:1213:1213))
        (PORT datab (2053:2053:2053) (2053:2053:2053))
        (PORT datac (564:564:564) (564:564:564))
        (PORT datad (771:771:771) (771:771:771))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH datab regin (607:607:607) (607:607:607))
        (IOPATH datac regin (478:478:478) (478:478:478))
        (IOPATH datad regin (309:309:309) (309:309:309))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\led_8\[2\]\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (5058:5058:5058) (5058:5058:5058))
        (PORT clk (4721:4721:4721) (4721:4721:4721))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\Equal1\~42\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (550:550:550) (550:550:550))
        (PORT datab (748:748:748) (748:748:748))
        (PORT datac (1227:1227:1227) (1227:1227:1227))
        (PORT datad (773:773:773) (773:773:773))
        (IOPATH dataa combout (590:590:590) (590:590:590))
        (IOPATH datab combout (442:442:442) (442:442:442))
        (IOPATH datac combout (292:292:292) (292:292:292))
        (IOPATH datad combout (114:114:114) (114:114:114))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\led_5\[0\]\~288\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datac (1356:1356:1356) (1356:1356:1356))
        (PORT datad (1212:1212:1212) (1212:1212:1212))
        (IOPATH datac combout (292:292:292) (292:292:292))
        (IOPATH datad combout (114:114:114) (114:114:114))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\led_7\[0\]\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datac (593:593:593) (593:593:593))
        (IOPATH datac regin (478:478:478) (478:478:478))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\led_7\[0\]\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (5058:5058:5058) (5058:5058:5058))
        (PORT clk (4721:4721:4721) (4721:4721:4721))
        (PORT ena (1323:1323:1323) (1323:1323:1323))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP ena (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD ena (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\led_7\[2\]\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (690:690:690) (690:690:690))
        (PORT datab (558:558:558) (558:558:558))
        (PORT datac (593:593:593) (593:593:593))
        (PORT datad (576:576:576) (576:576:576))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH datab regin (607:607:607) (607:607:607))
        (IOPATH datac regin (478:478:478) (478:478:478))
        (IOPATH datad regin (309:309:309) (309:309:309))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\led_7\[2\]\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (5058:5058:5058) (5058:5058:5058))
        (PORT clk (4721:4721:4721) (4721:4721:4721))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\led_7\[3\]\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (588:588:588) (588:588:588))
        (PORT datab (554:554:554) (554:554:554))
        (PORT datac (575:575:575) (575:575:575))
        (PORT datad (585:585:585) (585:585:585))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH datab regin (607:607:607) (607:607:607))
        (IOPATH datac regin (478:478:478) (478:478:478))
        (IOPATH datad regin (309:309:309) (309:309:309))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\led_7\[3\]\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (5058:5058:5058) (5058:5058:5058))
        (PORT clk (4721:4721:4721) (4721:4721:4721))
        (PORT ena (1323:1323:1323) (1323:1323:1323))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP ena (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD ena (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\led_7\[1\]\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (593:593:593) (593:593:593))
        (PORT datab (546:546:546) (546:546:546))
        (PORT datac (578:578:578) (578:578:578))
        (PORT datad (591:591:591) (591:591:591))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH datab regin (607:607:607) (607:607:607))
        (IOPATH datac regin (478:478:478) (478:478:478))
        (IOPATH datad regin (309:309:309) (309:309:309))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\led_7\[1\]\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (5058:5058:5058) (5058:5058:5058))
        (PORT clk (4721:4721:4721) (4721:4721:4721))
        (PORT ena (1323:1323:1323) (1323:1323:1323))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP ena (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD ena (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\Equal2\~42\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1178:1178:1178) (1178:1178:1178))
        (PORT datab (750:750:750) (750:750:750))
        (PORT datac (788:788:788) (788:788:788))
        (PORT datad (761:761:761) (761:761:761))
        (IOPATH dataa combout (590:590:590) (590:590:590))
        (IOPATH datab combout (442:442:442) (442:442:442))
        (IOPATH datac combout (292:292:292) (292:292:292))
        (IOPATH datad combout (114:114:114) (114:114:114))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\led_6\[0\]\~258\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1346:1346:1346) (1346:1346:1346))
        (PORT datac (1202:1202:1202) (1202:1202:1202))
        (PORT datad (1214:1214:1214) (1214:1214:1214))
        (IOPATH dataa combout (590:590:590) (590:590:590))
        (IOPATH datac combout (292:292:292) (292:292:292))
        (IOPATH datad combout (114:114:114) (114:114:114))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\led_6\[0\]\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datac (606:606:606) (606:606:606))
        (IOPATH datac regin (478:478:478) (478:478:478))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\led_6\[0\]\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (5058:5058:5058) (5058:5058:5058))
上一页 1 2 3 45
💿 文件大小 414 K
👤 上传用户 qq735970242
📂 所属分类 VHDL/FPGA/Verilog
🏷️ 相关标签

#CYCLONE #144C #FPGA #T144
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