📄 sec_clock_vhd.sdo

📁 基于CYCLONE系列FPGA EP1C3T144C8的VHDL秒表代码
💻 SDO
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// Copyright (C) 1991-2007 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.


// 
// Device: Altera EP1C3T144C8 Package TQFP144
// 

// 
// This SDF file should be used for ModelSim (VHDL) only
// 

(DELAYFILE
  (SDFVERSION "2.1")
  (DESIGN "sec_clock")
  (DATE "10/08/2008 20:20:16")
  (VENDOR "Altera")
  (PROGRAM "Quartus II")
  (VERSION "Version 7.2 Build 151 09/26/2007 SJ Full Version")
  (DIVIDER .)
  (TIMESCALE 1 ps)

  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\num\[16\]\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (534:534:534) (534:534:534))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH cin regin (839:839:839) (839:839:839))
        (IOPATH cin0 regin (783:783:783) (783:783:783))
        (IOPATH cin1 regin (787:787:787) (787:787:787))
        (IOPATH dataa cout0 (564:564:564) (564:564:564))
        (IOPATH cin0 cout0 (78:78:78) (78:78:78))
        (IOPATH dataa cout1 (575:575:575) (575:575:575))
        (IOPATH cin1 cout1 (80:80:80) (80:80:80))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\num\[16\]\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (2347:2347:2347) (2347:2347:2347))
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (1261:1261:1261) (1261:1261:1261))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP sclr (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD sclr (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\num\[17\]\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (507:507:507) (507:507:507))
        (IOPATH datab regin (607:607:607) (607:607:607))
        (IOPATH cin regin (839:839:839) (839:839:839))
        (IOPATH cin0 regin (783:783:783) (783:783:783))
        (IOPATH cin1 regin (787:787:787) (787:787:787))
        (IOPATH datab cout0 (423:423:423) (423:423:423))
        (IOPATH cin0 cout0 (78:78:78) (78:78:78))
        (IOPATH datab cout1 (432:432:432) (432:432:432))
        (IOPATH cin1 cout1 (80:80:80) (80:80:80))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\num\[17\]\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (2347:2347:2347) (2347:2347:2347))
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (1261:1261:1261) (1261:1261:1261))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP sclr (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD sclr (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\num\[0\]\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (542:542:542) (542:542:542))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH dataa cout0 (564:564:564) (564:564:564))
        (IOPATH dataa cout1 (575:575:575) (575:575:575))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\num\[0\]\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (1830:1830:1830) (1830:1830:1830))
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (1261:1261:1261) (1261:1261:1261))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP sclr (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD sclr (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\num\[1\]\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (546:546:546) (546:546:546))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH cin0 regin (783:783:783) (783:783:783))
        (IOPATH cin1 regin (787:787:787) (787:787:787))
        (IOPATH dataa cout0 (564:564:564) (564:564:564))
        (IOPATH cin0 cout0 (78:78:78) (78:78:78))
        (IOPATH dataa cout1 (575:575:575) (575:575:575))
        (IOPATH cin1 cout1 (80:80:80) (80:80:80))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\num\[1\]\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (1830:1830:1830) (1830:1830:1830))
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (1261:1261:1261) (1261:1261:1261))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP sclr (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD sclr (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\num\[2\]\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (520:520:520) (520:520:520))
        (IOPATH datab regin (607:607:607) (607:607:607))
        (IOPATH cin0 regin (783:783:783) (783:783:783))
        (IOPATH cin1 regin (787:787:787) (787:787:787))
        (IOPATH datab cout0 (423:423:423) (423:423:423))
        (IOPATH cin0 cout0 (78:78:78) (78:78:78))
        (IOPATH datab cout1 (432:432:432) (432:432:432))
        (IOPATH cin1 cout1 (80:80:80) (80:80:80))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\num\[2\]\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (1830:1830:1830) (1830:1830:1830))
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (1261:1261:1261) (1261:1261:1261))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP sclr (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD sclr (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\num\[3\]\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (520:520:520) (520:520:520))
        (IOPATH datab regin (607:607:607) (607:607:607))
        (IOPATH cin0 regin (783:783:783) (783:783:783))
        (IOPATH cin1 regin (787:787:787) (787:787:787))
        (IOPATH datab cout (583:583:583) (583:583:583))
        (IOPATH cin0 cout (178:178:178) (178:178:178))
        (IOPATH cin1 cout (157:157:157) (157:157:157))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\num\[3\]\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (1830:1830:1830) (1830:1830:1830))
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (1261:1261:1261) (1261:1261:1261))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP sclr (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD sclr (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\num\[4\]\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (508:508:508) (508:508:508))
        (IOPATH datab regin (607:607:607) (607:607:607))
        (IOPATH cin regin (839:839:839) (839:839:839))
        (IOPATH datab cout0 (423:423:423) (423:423:423))
        (IOPATH datab cout1 (432:432:432) (432:432:432))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\num\[4\]\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (1830:1830:1830) (1830:1830:1830))
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (1261:1261:1261) (1261:1261:1261))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP sclr (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD sclr (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\num\[5\]\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (534:534:534) (534:534:534))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH cin regin (839:839:839) (839:839:839))
        (IOPATH cin0 regin (783:783:783) (783:783:783))
        (IOPATH cin1 regin (787:787:787) (787:787:787))
        (IOPATH dataa cout0 (564:564:564) (564:564:564))
        (IOPATH cin0 cout0 (78:78:78) (78:78:78))
        (IOPATH dataa cout1 (575:575:575) (575:575:575))
        (IOPATH cin1 cout1 (80:80:80) (80:80:80))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\num\[5\]\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (1830:1830:1830) (1830:1830:1830))
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (1261:1261:1261) (1261:1261:1261))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP sclr (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD sclr (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\num\[6\]\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (538:538:538) (538:538:538))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH cin regin (839:839:839) (839:839:839))
        (IOPATH cin0 regin (783:783:783) (783:783:783))
        (IOPATH cin1 regin (787:787:787) (787:787:787))
        (IOPATH dataa cout0 (564:564:564) (564:564:564))
        (IOPATH cin0 cout0 (78:78:78) (78:78:78))
        (IOPATH dataa cout1 (575:575:575) (575:575:575))
        (IOPATH cin1 cout1 (80:80:80) (80:80:80))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\num\[6\]\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (1830:1830:1830) (1830:1830:1830))
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (1261:1261:1261) (1261:1261:1261))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP sclr (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD sclr (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\num\[7\]\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (514:514:514) (514:514:514))
        (IOPATH datab regin (607:607:607) (607:607:607))
        (IOPATH cin regin (839:839:839) (839:839:839))
        (IOPATH cin0 regin (783:783:783) (783:783:783))
        (IOPATH cin1 regin (787:787:787) (787:787:787))
        (IOPATH datab cout0 (423:423:423) (423:423:423))
        (IOPATH cin0 cout0 (78:78:78) (78:78:78))
        (IOPATH datab cout1 (432:432:432) (432:432:432))
        (IOPATH cin1 cout1 (80:80:80) (80:80:80))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\num\[7\]\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (1830:1830:1830) (1830:1830:1830))
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (1261:1261:1261) (1261:1261:1261))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP sclr (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD sclr (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\num\[8\]\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (539:539:539) (539:539:539))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH cin regin (839:839:839) (839:839:839))
        (IOPATH cin0 regin (783:783:783) (783:783:783))
        (IOPATH cin1 regin (787:787:787) (787:787:787))
        (IOPATH dataa cout (838:838:838) (838:838:838))
        (IOPATH cin cout (208:208:208) (208:208:208))
        (IOPATH cin0 cout (271:271:271) (271:271:271))
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💿 文件大小 414 K
👤 上传用户 qq735970242
📂 所属分类 VHDL/FPGA/Verilog
🏷️ 相关标签

#CYCLONE #144C #FPGA #T144
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