sec_clock_modelsim.xrf

基于CYCLONE系列FPGA EP1C3T144C8的VHDL秒表代码

vendor_name = ModelSim
source_file = 1, D:/MY_FILES/sec_clock/sec_clock.vhd
design_name = sec_clock
instance = comp, \num[16]\, num[16], sec_clock, 1
instance = comp, \num[17]\, num[17], sec_clock, 1
instance = comp, \num[0]\, num[0], sec_clock, 1
instance = comp, \num[1]\, num[1], sec_clock, 1
instance = comp, \num[2]\, num[2], sec_clock, 1
instance = comp, \num[3]\, num[3], sec_clock, 1
instance = comp, \num[4]\, num[4], sec_clock, 1
instance = comp, \num[5]\, num[5], sec_clock, 1
instance = comp, \num[6]\, num[6], sec_clock, 1
instance = comp, \num[7]\, num[7], sec_clock, 1
instance = comp, \num[8]\, num[8], sec_clock, 1
instance = comp, \num[9]\, num[9], sec_clock, 1
instance = comp, \num[10]\, num[10], sec_clock, 1
instance = comp, \num[11]\, num[11], sec_clock, 1
instance = comp, \num[12]\, num[12], sec_clock, 1
instance = comp, \num[13]\, num[13], sec_clock, 1
instance = comp, \num[14]\, num[14], sec_clock, 1
instance = comp, \num[15]\, num[15], sec_clock, 1
instance = comp, \num[18]\, num[18], sec_clock, 1
instance = comp, \LessThan0~279\, LessThan0~279, sec_clock, 1
instance = comp, \LessThan0~280\, LessThan0~280, sec_clock, 1
instance = comp, \LessThan0~281\, LessThan0~281, sec_clock, 1
instance = comp, \LessThan0~282\, LessThan0~282, sec_clock, 1
instance = comp, \LessThan0~283\, LessThan0~283, sec_clock, 1
instance = comp, \LessThan0~284\, LessThan0~284, sec_clock, 1
instance = comp, \LessThan0~285\, LessThan0~285, sec_clock, 1
instance = comp, \clk~I\, clk, sec_clock, 1
instance = comp, \start~I\, start, sec_clock, 1
instance = comp, \rst~I\, rst, sec_clock, 1
instance = comp, \Add2~162\, Add2~162, sec_clock, 1
instance = comp, \P2:scan[0]\, \P2:scan[0], sec_clock, 1
instance = comp, \Add2~164\, Add2~164, sec_clock, 1
instance = comp, \P2:scan[1]\, \P2:scan[1], sec_clock, 1
instance = comp, \Add2~166\, Add2~166, sec_clock, 1
instance = comp, \P2:scan[2]\, \P2:scan[2], sec_clock, 1
instance = comp, \Add2~168\, Add2~168, sec_clock, 1
instance = comp, \P2:scan[3]\, \P2:scan[3], sec_clock, 1
instance = comp, \Add2~174\, Add2~174, sec_clock, 1
instance = comp, \P2:scan[4]\, \P2:scan[4], sec_clock, 1
instance = comp, \Add2~176\, Add2~176, sec_clock, 1
instance = comp, \P2:scan[5]\, \P2:scan[5], sec_clock, 1
instance = comp, \Add2~170\, Add2~170, sec_clock, 1
instance = comp, \P2:scan[6]\, \P2:scan[6], sec_clock, 1
instance = comp, \Add2~172\, Add2~172, sec_clock, 1
instance = comp, \P2:scan[7]\, \P2:scan[7], sec_clock, 1
instance = comp, \Add2~178\, Add2~178, sec_clock, 1
instance = comp, \P2:scan[8]\, \P2:scan[8], sec_clock, 1
instance = comp, \Add2~180\, Add2~180, sec_clock, 1
instance = comp, \P2:scan[9]\, \P2:scan[9], sec_clock, 1
instance = comp, \Add2~182\, Add2~182, sec_clock, 1
instance = comp, \P2:scan[10]\, \P2:scan[10], sec_clock, 1
instance = comp, \Equal0~100\, Equal0~100, sec_clock, 1
instance = comp, \Equal0~101\, Equal0~101, sec_clock, 1
instance = comp, \seclect[0]\, seclect[0], sec_clock, 1
instance = comp, \seclect[1]\, seclect[1], sec_clock, 1
instance = comp, \seclect[2]\, seclect[2], sec_clock, 1
instance = comp, \Equal18~84\, Equal18~84, sec_clock, 1
instance = comp, \Equal18~85\, Equal18~85, sec_clock, 1
instance = comp, \Equal18~86\, Equal18~86, sec_clock, 1
instance = comp, \Equal18~87\, Equal18~87, sec_clock, 1
instance = comp, \Equal18~88\, Equal18~88, sec_clock, 1
instance = comp, \sel~111\, sel~111, sec_clock, 1
instance = comp, \Equal18~89\, Equal18~89, sec_clock, 1
instance = comp, \Equal18~90\, Equal18~90, sec_clock, 1
instance = comp, \led_8[0]\, led_8[0], sec_clock, 1
instance = comp, \led_8[3]\, led_8[3], sec_clock, 1
instance = comp, \led_8[1]\, led_8[1], sec_clock, 1
instance = comp, \led_8[2]\, led_8[2], sec_clock, 1
instance = comp, \Equal1~42\, Equal1~42, sec_clock, 1
instance = comp, \led_5[0]~288\, led_5[0]~288, sec_clock, 1
instance = comp, \led_7[0]\, led_7[0], sec_clock, 1
instance = comp, \led_7[2]\, led_7[2], sec_clock, 1
instance = comp, \led_7[3]\, led_7[3], sec_clock, 1
instance = comp, \led_7[1]\, led_7[1], sec_clock, 1
instance = comp, \Equal2~42\, Equal2~42, sec_clock, 1
instance = comp, \led_6[0]~258\, led_6[0]~258, sec_clock, 1
instance = comp, \led_6[0]\, led_6[0], sec_clock, 1
instance = comp, \led_6[2]\, led_6[2], sec_clock, 1
instance = comp, \led_6[3]\, led_6[3], sec_clock, 1
instance = comp, \led_6[1]\, led_6[1], sec_clock, 1
instance = comp, \Equal3~42\, Equal3~42, sec_clock, 1
instance = comp, \led_5[0]~290\, led_5[0]~290, sec_clock, 1
instance = comp, \led_5[0]\, led_5[0], sec_clock, 1
instance = comp, \led_5[2]\, led_5[2], sec_clock, 1
instance = comp, \led_5[3]~291\, led_5[3]~291, sec_clock, 1
instance = comp, \led_5[3]\, led_5[3], sec_clock, 1
instance = comp, \led_5[1]\, led_5[1], sec_clock, 1
instance = comp, \Equal4~42\, Equal4~42, sec_clock, 1
instance = comp, \led_4~630\, led_4~630, sec_clock, 1
instance = comp, \led_4[0]\, led_4[0], sec_clock, 1
instance = comp, \Equal5~46\, Equal5~46, sec_clock, 1
instance = comp, \led_2~361\, led_2~361, sec_clock, 1
instance = comp, \led_4[3]\, led_4[3], sec_clock, 1
instance = comp, \led_4[1]~634\, led_4[1]~634, sec_clock, 1
instance = comp, \led_4[1]\, led_4[1], sec_clock, 1
instance = comp, \led_4~631\, led_4~631, sec_clock, 1
instance = comp, \led_4[2]\, led_4[2], sec_clock, 1
instance = comp, \led_3[0]\, led_3[0], sec_clock, 1
instance = comp, \led_3[1]~421\, led_3[1]~421, sec_clock, 1
instance = comp, \led_3[1]\, led_3[1], sec_clock, 1
instance = comp, \led_3~418\, led_3~418, sec_clock, 1
instance = comp, \led_3[2]\, led_3[2], sec_clock, 1
instance = comp, \led_3[3]\, led_3[3], sec_clock, 1
instance = comp, \Equal6~39\, Equal6~39, sec_clock, 1
instance = comp, \led_1[1]~139\, led_1[1]~139, sec_clock, 1
instance = comp, \led_2[0]\, led_2[0], sec_clock, 1
instance = comp, \led_2~364\, led_2~364, sec_clock, 1
instance = comp, \led_2[3]\, led_2[3], sec_clock, 1
instance = comp, \Equal7~39\, Equal7~39, sec_clock, 1
instance = comp, \led_2[1]\, led_2[1], sec_clock, 1
instance = comp, \led_2~362\, led_2~362, sec_clock, 1
instance = comp, \led_2[2]\, led_2[2], sec_clock, 1
instance = comp, \led_1[0]\, led_1[0], sec_clock, 1
instance = comp, \led_1[1]\, led_1[1], sec_clock, 1
instance = comp, \led_1[1]~140\, led_1[1]~140, sec_clock, 1
instance = comp, \led_1[2]\, led_1[2], sec_clock, 1
instance = comp, \seg[2]~213\, seg[2]~213, sec_clock, 1
instance = comp, \seg[2]~214\, seg[2]~214, sec_clock, 1
instance = comp, \seg[2]~211\, seg[2]~211, sec_clock, 1
instance = comp, \seg[2]~212\, seg[2]~212, sec_clock, 1
instance = comp, \seg[2]~215\, seg[2]~215, sec_clock, 1
instance = comp, \seg[0]~228\, seg[0]~228, sec_clock, 1
instance = comp, \seg[0]~229\, seg[0]~229, sec_clock, 1
instance = comp, \seg[0]~226\, seg[0]~226, sec_clock, 1
instance = comp, \seg[0]~227\, seg[0]~227, sec_clock, 1
instance = comp, \seg[0]~230\, seg[0]~230, sec_clock, 1
instance = comp, \seg[1]~223\, seg[1]~223, sec_clock, 1
instance = comp, \seg[1]~224\, seg[1]~224, sec_clock, 1
instance = comp, \seg[1]~221\, seg[1]~221, sec_clock, 1
instance = comp, \seg[1]~222\, seg[1]~222, sec_clock, 1
instance = comp, \seg[1]~225\, seg[1]~225, sec_clock, 1
instance = comp, \seg[3]~216\, seg[3]~216, sec_clock, 1
instance = comp, \seg[3]~217\, seg[3]~217, sec_clock, 1
instance = comp, \led_1[3]\, led_1[3], sec_clock, 1
instance = comp, \seg[3]~218\, seg[3]~218, sec_clock, 1
instance = comp, \seg[3]~219\, seg[3]~219, sec_clock, 1
instance = comp, \seg[3]~220\, seg[3]~220, sec_clock, 1
instance = comp, \data~1042\, data~1042, sec_clock, 1
instance = comp, \Equal17~235\, Equal17~235, sec_clock, 1
instance = comp, \Equal17~234\, Equal17~234, sec_clock, 1
instance = comp, \Equal17~236\, Equal17~236, sec_clock, 1
instance = comp, \data~1040\, data~1040, sec_clock, 1
instance = comp, \data~1041\, data~1041, sec_clock, 1
instance = comp, \data~1043\, data~1043, sec_clock, 1
instance = comp, \Equal17~241\, Equal17~241, sec_clock, 1
instance = comp, \Equal17~237\, Equal17~237, sec_clock, 1
instance = comp, \Equal17~240\, Equal17~240, sec_clock, 1
instance = comp, \Equal17~238\, Equal17~238, sec_clock, 1
instance = comp, \Equal17~239\, Equal17~239, sec_clock, 1
instance = comp, \data~1044\, data~1044, sec_clock, 1
instance = comp, \data~1045\, data~1045, sec_clock, 1
instance = comp, \data~1046\, data~1046, sec_clock, 1
instance = comp, \data~1047\, data~1047, sec_clock, 1
instance = comp, \data~1048\, data~1048, sec_clock, 1
instance = comp, \data~1049\, data~1049, sec_clock, 1
instance = comp, \data~1050\, data~1050, sec_clock, 1
instance = comp, \data~1051\, data~1051, sec_clock, 1
instance = comp, \data~1055\, data~1055, sec_clock, 1
instance = comp, \data~1052\, data~1052, sec_clock, 1
instance = comp, \data~1053\, data~1053, sec_clock, 1
instance = comp, \data~1054\, data~1054, sec_clock, 1
instance = comp, \sel[0]~I\, sel[0], sec_clock, 1
instance = comp, \sel[1]~I\, sel[1], sec_clock, 1
instance = comp, \sel[2]~I\, sel[2], sec_clock, 1
instance = comp, \sel[3]~I\, sel[3], sec_clock, 1
instance = comp, \sel[4]~I\, sel[4], sec_clock, 1
instance = comp, \sel[5]~I\, sel[5], sec_clock, 1
instance = comp, \sel[6]~I\, sel[6], sec_clock, 1
instance = comp, \sel[7]~I\, sel[7], sec_clock, 1
instance = comp, \data[0]~I\, data[0], sec_clock, 1
instance = comp, \data[1]~I\, data[1], sec_clock, 1
instance = comp, \data[2]~I\, data[2], sec_clock, 1
instance = comp, \data[3]~I\, data[3], sec_clock, 1
instance = comp, \data[4]~I\, data[4], sec_clock, 1
instance = comp, \data[5]~I\, data[5], sec_clock, 1
instance = comp, \data[6]~I\, data[6], sec_clock, 1
instance = comp, \data[7]~I\, data[7], sec_clock, 1