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📄 sec_clock.vho

📁 基于CYCLONE系列FPGA EP1C3T144C8的VHDL秒表代码
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	operation_mode => "normal",
	output_mode => "comb_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	datab => seclect(0),
	datac => seclect(1),
	datad => seclect(2),
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \Equal18~90_combout\);

rst1 : cyclone_lcell
-- Equation(s):
-- \rst1~regout\ = DFFEAS(!\rst1~regout\, \rst~combout\, VCC, , , , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "00ff",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => \rst~combout\,
	datad => \rst1~regout\,
	aclr => GND,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \rst1~regout\);

start1 : cyclone_lcell
-- Equation(s):
-- \start1~regout\ = DFFEAS(!\start1~regout\, !\start~combout\, VCC, , , , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "00ff",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => \ALT_INV_start~combout\,
	datad => \start1~regout\,
	aclr => GND,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \start1~regout\);

\led_8[0]\ : cyclone_lcell
-- Equation(s):
-- led_8(0) = DFFEAS(!led_8(0), GLOBAL(\clk1~regout\), GLOBAL(\rst1~regout\), , \start1~regout\, , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0f0f",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => \clk1~regout\,
	datac => led_8(0),
	aclr => \ALT_INV_rst1~regout\,
	ena => \start1~regout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => led_8(0));

\led_8[3]\ : cyclone_lcell
-- Equation(s):
-- led_8(3) = DFFEAS(led_8(3) & (led_8(1) $ led_8(2) # !led_8(0)) # !led_8(3) & led_8(1) & led_8(0) & led_8(2), GLOBAL(\clk1~regout\), GLOBAL(\rst1~regout\), , \start1~regout\, , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "6a8a",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => \clk1~regout\,
	dataa => led_8(3),
	datab => led_8(1),
	datac => led_8(0),
	datad => led_8(2),
	aclr => \ALT_INV_rst1~regout\,
	ena => \start1~regout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => led_8(3));

\led_8[1]\ : cyclone_lcell
-- Equation(s):
-- led_8(1) = DFFEAS(led_8(1) & (!led_8(0)) # !led_8(1) & led_8(0) & (led_8(2) # !led_8(3)), GLOBAL(\clk1~regout\), GLOBAL(\rst1~regout\), , \start1~regout\, , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "3c1c",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => \clk1~regout\,
	dataa => led_8(3),
	datab => led_8(1),
	datac => led_8(0),
	datad => led_8(2),
	aclr => \ALT_INV_rst1~regout\,
	ena => \start1~regout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => led_8(1));

\led_8[2]\ : cyclone_lcell
-- Equation(s):
-- led_8(2) = DFFEAS(led_8(2) $ (led_8(0) & \start1~regout\ & led_8(1)), GLOBAL(\clk1~regout\), GLOBAL(\rst1~regout\), , , , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "78f0",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => \clk1~regout\,
	dataa => led_8(0),
	datab => \start1~regout\,
	datac => led_8(2),
	datad => led_8(1),
	aclr => \ALT_INV_rst1~regout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => led_8(2));

\Equal1~42\ : cyclone_lcell
-- Equation(s):
-- \Equal1~42_combout\ = !led_8(2) & led_8(3) & led_8(0) & !led_8(1)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0040",
	operation_mode => "normal",
	output_mode => "comb_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	dataa => led_8(2),
	datab => led_8(3),
	datac => led_8(0),
	datad => led_8(1),
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \Equal1~42_combout\);

\led_5[0]~288\ : cyclone_lcell
-- Equation(s):
-- \led_5[0]~288_combout\ = \start1~regout\ & \Equal1~42_combout\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "f000",
	operation_mode => "normal",
	output_mode => "comb_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	datac => \start1~regout\,
	datad => \Equal1~42_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \led_5[0]~288_combout\);

\led_7[0]\ : cyclone_lcell
-- Equation(s):
-- led_7(0) = DFFEAS(!led_7(0), GLOBAL(\clk1~regout\), GLOBAL(\rst1~regout\), , \led_5[0]~288_combout\, , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0f0f",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => \clk1~regout\,
	datac => led_7(0),
	aclr => \ALT_INV_rst1~regout\,
	ena => \led_5[0]~288_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => led_7(0));

\led_7[2]\ : cyclone_lcell
-- Equation(s):
-- led_7(2) = DFFEAS(led_7(2) $ (\led_5[0]~288_combout\ & led_7(0) & led_7(1)), GLOBAL(\clk1~regout\), GLOBAL(\rst1~regout\), , , , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "6ccc",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => \clk1~regout\,
	dataa => \led_5[0]~288_combout\,
	datab => led_7(2),
	datac => led_7(0),
	datad => led_7(1),
	aclr => \ALT_INV_rst1~regout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => led_7(2));

\led_7[3]\ : cyclone_lcell
-- Equation(s):
-- led_7(3) = DFFEAS(led_7(0) & (led_7(1) & (led_7(3) $ led_7(2)) # !led_7(1) & led_7(3) & led_7(2)) # !led_7(0) & (led_7(3)), GLOBAL(\clk1~regout\), GLOBAL(\rst1~regout\), , \led_5[0]~288_combout\, , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "78d0",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => \clk1~regout\,
	dataa => led_7(0),
	datab => led_7(1),
	datac => led_7(3),
	datad => led_7(2),
	aclr => \ALT_INV_rst1~regout\,
	ena => \led_5[0]~288_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => led_7(3));

\led_7[1]\ : cyclone_lcell
-- Equation(s):
-- led_7(1) = DFFEAS(led_7(0) & !led_7(1) & (led_7(2) # !led_7(3)) # !led_7(0) & led_7(1), GLOBAL(\clk1~regout\), GLOBAL(\rst1~regout\), , \led_5[0]~288_combout\, , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "6646",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => \clk1~regout\,
	dataa => led_7(0),
	datab => led_7(1),
	datac => led_7(3),
	datad => led_7(2),
	aclr => \ALT_INV_rst1~regout\,
	ena => \led_5[0]~288_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => led_7(1));

\Equal2~42\ : cyclone_lcell
-- Equation(s):
-- \Equal2~42_combout\ = !led_7(1) & led_7(3) & !led_7(2) & led_7(0)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0400",
	operation_mode => "normal",
	output_mode => "comb_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	dataa => led_7(1),
	datab => led_7(3),
	datac => led_7(2),
	datad => led_7(0),
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \Equal2~42_combout\);

\led_6[0]~258\ : cyclone_lcell
-- Equation(s):
-- \led_6[0]~258_combout\ = \start1~regout\ & (\Equal2~42_combout\ & \Equal1~42_combout\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "a000",
	operation_mode => "normal",
	output_mode => "comb_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	dataa => \start1~regout\,
	datac => \Equal2~42_combout\,
	datad => \Equal1~42_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \led_6[0]~258_combout\);

\led_6[0]\ : cyclone_lcell
-- Equation(s):
-- led_6(0) = DFFEAS(!led_6(0), GLOBAL(\clk1~regout\), GLOBAL(\rst1~regout\), , \led_6[0]~258_combout\, , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0f0f",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => \clk1~regout\,
	datac => led_6(0),
	aclr => \ALT_INV_rst1~regout\,
	ena => \led_6[0]~258_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => led_6(0));

\led_6[2]\ : cyclone_lcell
-- Equation(s):
-- led_6(2) = DFFEAS(led_6(2) $ (led_6(0) & led_6(1) & \led_6[0]~258_combout\), GLOBAL(\clk1~regout\), GLOBAL(\rst1~regout\), , , , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "7f80",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => \clk1~regout\,
	dataa => led_6(0),
	datab => led_6(1),
	datac => \led_6[0]~258_combout\,
	datad => led_6(2),
	aclr => \ALT_INV_rst1~regout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => led_6(2));

\led_6[3]\ : cyclone_lcell
-- Equation(s):
-- led_6(3) = DFFEAS(led_6(0) & (led_6(3) & (led_6(1) $ led_6(2)) # !led_6(3) & led_6(1) & led_6(2)) # !led_6(0) & led_6(3), GLOBAL(\clk1~regout\), GLOBAL(\rst1~regout\), , \led_6[0]~258_combout\, , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "6cc4",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => \clk1~regout\,
	dataa => led_6(0),
	datab => led_6(3),
	datac => led_6(1),
	datad => led_6(2),
	aclr => \ALT_INV_rst1~regout\,
	ena => \led_6[0]~258_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => led_6(3));

\led_6[1]\ : cyclone_lcell
-- Equation(s):
-- led_6(1) = DFFEAS(led_6(0) & !led_6(1) & (led_6(2) # !led_6(3)) # !led_6(0) & (led_6(1)), GLOBAL(\clk1~regout\), GLOBAL(\rst1~regout\), , \led_6[0]~258_combout\, , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "5a52",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => \clk1~regout\,
	dataa => led_6(0),
	datab => led_6(3),
	datac => led_6(1),
	datad => led_6(2),
	aclr => \ALT_INV_rst1~regout\,
	ena => \led_6[0]~258_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => led_6(1));

\Equal3~42\ : cyclone_lcell
-- Equation(s):
-- \Equal3~42_combout\ = !led_6(1) & led_6(3) & led_6(0) & !led_6(2)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0040",
	operation_mode => "normal",
	output_mode => "comb_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	dataa => led_6(1),
	datab => led_6(3),
	datac => led_6(0),
	datad => led_6(2),
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \Equal3~42_combout\);

\led_5[0]~290\ : cyclone_lcell
-- Equation(s):
-- \led_5[0]~290_combout\ = \start1~regout\ & \Equal3~42_combout\ & \Equal2~42_combout\ & \Equal1~42_combout\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "8000",
	operation_mode => "normal",
	output_mode => "comb_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	dataa => \start1~r
12345

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