sec_clock.vho

基于CYCLONE系列FPGA EP1C3T144C8的VHDL秒表代码

PORT MAP (
	clk => \clk~combout\,
	datac => \Equal0~101_combout\,
	datad => \Add2~170_combout\,
	aclr => GND,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \P2:scan[6]~regout\);

\Add2~172\ : cyclone_lcell
-- Equation(s):
-- \Add2~172_combout\ = \P2:scan[7]~regout\ $ ((!\Add2~175\ & \Add2~171\) # (\Add2~175\ & \Add2~171COUT1\))
-- \Add2~173\ = CARRY(!\Add2~171\ # !\P2:scan[7]~regout\)
-- \Add2~173COUT1\ = CARRY(!\Add2~171COUT1\ # !\P2:scan[7]~regout\)

-- pragma translate_off
GENERIC MAP (
	cin0_used => "true",
	cin1_used => "true",
	cin_used => "true",
	lut_mask => "5a5f",
	operation_mode => "arithmetic",
	output_mode => "comb_only",
	register_cascade_mode => "off",
	sum_lutc_input => "cin",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	dataa => \P2:scan[7]~regout\,
	cin => \Add2~175\,
	cin0 => \Add2~171\,
	cin1 => \Add2~171COUT1\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \Add2~172_combout\,
	cout0 => \Add2~173\,
	cout1 => \Add2~173COUT1\);

\P2:scan[7]\ : cyclone_lcell
-- Equation(s):
-- \P2:scan[7]~regout\ = DFFEAS(\Add2~172_combout\ & (!\Equal0~101_combout\), GLOBAL(\clk~combout\), VCC, , , , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0a0a",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => \clk~combout\,
	dataa => \Add2~172_combout\,
	datac => \Equal0~101_combout\,
	aclr => GND,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \P2:scan[7]~regout\);

\Add2~178\ : cyclone_lcell
-- Equation(s):
-- \Add2~178_combout\ = \P2:scan[8]~regout\ $ !(!\Add2~175\ & \Add2~173\) # (\Add2~175\ & \Add2~173COUT1\)
-- \Add2~179\ = CARRY(\P2:scan[8]~regout\ & !\Add2~173\)
-- \Add2~179COUT1\ = CARRY(\P2:scan[8]~regout\ & !\Add2~173COUT1\)

-- pragma translate_off
GENERIC MAP (
	cin0_used => "true",
	cin1_used => "true",
	cin_used => "true",
	lut_mask => "c30c",
	operation_mode => "arithmetic",
	output_mode => "comb_only",
	register_cascade_mode => "off",
	sum_lutc_input => "cin",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	datab => \P2:scan[8]~regout\,
	cin => \Add2~175\,
	cin0 => \Add2~173\,
	cin1 => \Add2~173COUT1\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \Add2~178_combout\,
	cout0 => \Add2~179\,
	cout1 => \Add2~179COUT1\);

\P2:scan[8]\ : cyclone_lcell
-- Equation(s):
-- \P2:scan[8]~regout\ = DFFEAS(!\Equal0~101_combout\ & (\Add2~178_combout\), GLOBAL(\clk~combout\), VCC, , , , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "5050",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => \clk~combout\,
	dataa => \Equal0~101_combout\,
	datac => \Add2~178_combout\,
	aclr => GND,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \P2:scan[8]~regout\);

\Add2~180\ : cyclone_lcell
-- Equation(s):
-- \Add2~180_combout\ = \P2:scan[9]~regout\ $ (!\Add2~175\ & \Add2~179\) # (\Add2~175\ & \Add2~179COUT1\)
-- \Add2~181\ = CARRY(!\Add2~179COUT1\ # !\P2:scan[9]~regout\)

-- pragma translate_off
GENERIC MAP (
	cin0_used => "true",
	cin1_used => "true",
	cin_used => "true",
	lut_mask => "3c3f",
	operation_mode => "arithmetic",
	output_mode => "comb_only",
	register_cascade_mode => "off",
	sum_lutc_input => "cin",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	datab => \P2:scan[9]~regout\,
	cin => \Add2~175\,
	cin0 => \Add2~179\,
	cin1 => \Add2~179COUT1\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \Add2~180_combout\,
	cout => \Add2~181\);

\P2:scan[9]\ : cyclone_lcell
-- Equation(s):
-- \P2:scan[9]~regout\ = DFFEAS(!\Equal0~101_combout\ & \Add2~180_combout\, GLOBAL(\clk~combout\), VCC, , , , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0f00",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => \clk~combout\,
	datac => \Equal0~101_combout\,
	datad => \Add2~180_combout\,
	aclr => GND,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \P2:scan[9]~regout\);

\Add2~182\ : cyclone_lcell
-- Equation(s):
-- \Add2~182_combout\ = \P2:scan[10]~regout\ $ (!\Add2~181\)

-- pragma translate_off
GENERIC MAP (
	cin_used => "true",
	lut_mask => "a5a5",
	operation_mode => "normal",
	output_mode => "comb_only",
	register_cascade_mode => "off",
	sum_lutc_input => "cin",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	dataa => \P2:scan[10]~regout\,
	cin => \Add2~181\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \Add2~182_combout\);

\P2:scan[10]\ : cyclone_lcell
-- Equation(s):
-- \P2:scan[10]~regout\ = DFFEAS(!\Equal0~101_combout\ & \Add2~182_combout\, GLOBAL(\clk~combout\), VCC, , , , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0f00",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => \clk~combout\,
	datac => \Equal0~101_combout\,
	datad => \Add2~182_combout\,
	aclr => GND,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \P2:scan[10]~regout\);

\Equal0~100\ : cyclone_lcell
-- Equation(s):
-- \Equal0~100_combout\ = \P2:scan[10]~regout\ & \P2:scan[9]~regout\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "c0c0",
	operation_mode => "normal",
	output_mode => "comb_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	datab => \P2:scan[10]~regout\,
	datac => \P2:scan[9]~regout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \Equal0~100_combout\);

\Equal0~101\ : cyclone_lcell
-- Equation(s):
-- \Equal0~101_combout\ = \Equal0~100_combout\ & \Equal0~98\ & \P2:scan[8]~regout\ & \Equal0~99\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "8000",
	operation_mode => "normal",
	output_mode => "comb_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	dataa => \Equal0~100_combout\,
	datab => \Equal0~98\,
	datac => \P2:scan[8]~regout\,
	datad => \Equal0~99\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \Equal0~101_combout\);

\seclect[0]\ : cyclone_lcell
-- Equation(s):
-- seclect(0) = DFFEAS(\Equal0~101_combout\ $ seclect(0), GLOBAL(\clk~combout\), VCC, , , , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0ff0",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => \clk~combout\,
	datac => \Equal0~101_combout\,
	datad => seclect(0),
	aclr => GND,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => seclect(0));

\seclect[1]\ : cyclone_lcell
-- Equation(s):
-- seclect(1) = DFFEAS(seclect(1) $ (\Equal0~101_combout\ & seclect(0)), GLOBAL(\clk~combout\), VCC, , , , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "3ccc",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => \clk~combout\,
	datab => seclect(1),
	datac => \Equal0~101_combout\,
	datad => seclect(0),
	aclr => GND,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => seclect(1));

\seclect[2]\ : cyclone_lcell
-- Equation(s):
-- seclect(2) = DFFEAS(seclect(2) $ (seclect(0) & seclect(1) & \Equal0~101_combout\), GLOBAL(\clk~combout\), VCC, , , , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "7f80",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => \clk~combout\,
	dataa => seclect(0),
	datab => seclect(1),
	datac => \Equal0~101_combout\,
	datad => seclect(2),
	aclr => GND,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => seclect(2));

\Equal18~84\ : cyclone_lcell
-- Equation(s):
-- \Equal18~84_combout\ = seclect(0) & (seclect(1) & seclect(2))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "a000",
	operation_mode => "normal",
	output_mode => "comb_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	dataa => seclect(0),
	datac => seclect(1),
	datad => seclect(2),
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \Equal18~84_combout\);

\Equal18~85\ : cyclone_lcell
-- Equation(s):
-- \Equal18~85_combout\ = !seclect(0) & (seclect(1) & seclect(2))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "5000",
	operation_mode => "normal",
	output_mode => "comb_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	dataa => seclect(0),
	datac => seclect(1),
	datad => seclect(2),
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \Equal18~85_combout\);

\Equal18~86\ : cyclone_lcell
-- Equation(s):
-- \Equal18~86_combout\ = seclect(0) & (!seclect(1) & seclect(2))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0a00",
	operation_mode => "normal",
	output_mode => "comb_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	dataa => seclect(0),
	datac => seclect(1),
	datad => seclect(2),
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \Equal18~86_combout\);

\Equal18~87\ : cyclone_lcell
-- Equation(s):
-- \Equal18~87_combout\ = !seclect(0) & !seclect(1) & seclect(2)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0300",
	operation_mode => "normal",
	output_mode => "comb_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	datab => seclect(0),
	datac => seclect(1),
	datad => seclect(2),
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \Equal18~87_combout\);

\Equal18~88\ : cyclone_lcell
-- Equation(s):
-- \Equal18~88_combout\ = seclect(0) & seclect(1) & !seclect(2)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "00c0",
	operation_mode => "normal",
	output_mode => "comb_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	datab => seclect(0),
	datac => seclect(1),
	datad => seclect(2),
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \Equal18~88_combout\);

\sel~111\ : cyclone_lcell
-- Equation(s):
-- \sel~111_combout\ = !seclect(0) & seclect(1) & !seclect(2)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0030",
	operation_mode => "normal",
	output_mode => "comb_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	datab => seclect(0),
	datac => seclect(1),
	datad => seclect(2),
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \sel~111_combout\);

\Equal18~89\ : cyclone_lcell
-- Equation(s):
-- \Equal18~89_combout\ = seclect(0) & !seclect(1) & !seclect(2)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "000c",
	operation_mode => "normal",
	output_mode => "comb_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	datab => seclect(0),
	datac => seclect(1),
	datad => seclect(2),
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \Equal18~89_combout\);

\Equal18~90\ : cyclone_lcell
-- Equation(s):
-- \Equal18~90_combout\ = !seclect(0) & !seclect(1) & !seclect(2)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0003",