sec_clock.vhd.bak

基于CYCLONE系列FPGA EP1C3T144C8的VHDL秒表代码

library ieee;
use ieee.std_logic_1164.all;
entity sec_clock is
port( clk:in std_logic;
         rst:in std_logic;
	   start:in std_logic;
         sel:out std_logic_vector(7 downto 0);
       data:out std_logic_vector(7 downto 0));
end entity;
architecture min of sec_clock is
signal     clk1:std_logic;
signal     num:integer range 0 to 399999:=0;
signal  seclect:integer range 0 to 7 :=0;
signal    seg:integer range 0 to 9:=0;
signal led_1:integer range 0 to 9:=0;
signal led_2:integer range 0 to 9:=0;
signal led_3:integer range 0 to 9:=0;
signal led_4:integer range 0 to 9:=0;
signal led_5:integer range 0 to 9:=0;
signal led_6:integer range 0 to 9:=0;
signal led_7:integer range 0 to 9:=0;
signal led_8:integer range 0 to 9:=0;
signal   start1:std_logic:='0';
signal     rst1:std_logic:='0';

begin
--************分频器***********
P1:process(clk)
begin 
	if clk 'event and clk='1' then
		if num<199999 then
			num<=num+1;
		else
			num<=0;
			clk1<=not clk1;
		end if;
	end if;	
end process;
--************动态扫描**********
P2:process(clk)
variable scan:integer range 0 to 1999:=0;
begin
	if clk 'event and clk='1' then
		if scan=1999 then
			scan:=0;		
			if seclect<7 then
				seclect<=seclect+1;
			else
				seclect<=0;
			end if;
		else
			scan:=scan+1;
		end if;
	end if;
end process;
--************显示**********
P3:process(clk1,start1,rst1)
begin
	if rst1='1' then
	
	if(clk1 'event and clk1='1' and start1='1') then
		if(led_8=9) then
			led_8<=0;
			if(led_7=9) then
				led_7<=0;
				if(led_6=9) then
					led_6<=0;
					if(led_5=5) then
						led_5<=0;
						if(led_4=9) then	
							led_4<=0;
							if(led_3=5) then
								led_3<=0;
								if(led_2=9) then
									led_2<=0;
									led_1<=led_1+1;
								else
									led_2<=led_2+1;
								end if;								
 							else
	    						led_3<=led_3+1;
							end if;
						else
		   					led_4<=led_4+1;
						end if;
 					else
	    				led_5<=led_5+1;
					end if;
				else
  					led_6<=led_6+1;
				end if;
	 		else
				led_7<=led_7+1;
			end if;
		else
		   led_8<=led_8+1;
		end if;
	end if;
	else 
		led_1<=0;
		led_2<=0;
		led_3<=0;
		led_4<=0;
		led_5<=0;
		led_6<=0;
		led_7<=0;
		led_8<=0;
	end if;
end process;
--开始计时
P4:process(start)
begin
	if (start 'event and start='0') then
		start1<=not start1; 
	end if;
end process;

P5:process(rst)
begin
	if (rst 'event and rst='1') then
		rst1<=not rst1;
	end if;
end process;
seg <=led_1 when seclect=0 else
	      led_2 when seclect=1 else
	      led_3 when seclect=2 else
	      led_4 when seclect=3 else
	      led_5 when seclect=4 else
	      led_6 when seclect=5 else
	      led_7 when seclect=6 else
	      led_8 when seclect=7 else
	      0;

data <= "00111111" when seg=0 else
		    "00000110" when seg=1 else
		    "01011011" when seg=2 else
		    "01001111" when seg=3 else
		    "01100110" when seg=4 else
		    "01101101" when seg=5 else
		    "01111101" when seg=6 else
		    "00000111" when seg=7 else
		    "01111111" when seg=8 else
		    "01101111" when seg=9 else
		    "00000000";
		
sel <= "00000001" when seclect=7 else
		 "00000010" when seclect=6 else
		 "00000100" when seclect=5 else
		 "00001000" when seclect=4 else
		 "00010000" when seclect=3 else
		 "00100000" when seclect=2 else
		 "01000000" when seclect=1 else
		 "10000000" when seclect=0 else
        "00000000";
end architecture;