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📁 利用FPGA的资源实现任意波形的产生
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	lut_mask => "3CFC",
	clock_enable_mode => "false",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	datab => \inst|PASTEP[7]\,
	cin => \inst|add_rtl_5|adder|result_node|cout[0]\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \inst|add_rtl_5|adder|result_node|cs_buffer[1]\,
	cout => \inst|add_rtl_5|adder|result_node|cout[1]\);

\inst|add_rtl_4|adder|result_node|cs_buffer[1]~I\ : flex10ke_lcell
-- Equation(s):
-- \inst|add_rtl_4|adder|result_node|cs_buffer[1]\ = \inst|PASTEP[7]\ $ \inst|add_rtl_4|adder|result_node|cout[0]\
-- \inst|add_rtl_4|adder|result_node|cout[1]\ = CARRY(\inst|PASTEP[7]\ & \inst|add_rtl_4|adder|result_node|cout[0]\)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "arithmetic",
	cin_used => "true",
	packed_mode => "false",
	lut_mask => "3CC0",
	clock_enable_mode => "false",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	datab => \inst|PASTEP[7]\,
	cin => \inst|add_rtl_4|adder|result_node|cout[0]\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \inst|add_rtl_4|adder|result_node|cs_buffer[1]\,
	cout => \inst|add_rtl_4|adder|result_node|cout[1]\);

\inst|PASTEP[7]~I\ : flex10ke_lcell
-- Equation(s):
-- \inst|PASTEP[7]\ = DFFEA(\FreDec~dataout\ & (\inst|add_rtl_4|adder|result_node|cs_buffer[1]\) # !\FreDec~dataout\ & !\inst|add_rtl_5|adder|result_node|cs_buffer[1]\, \inst|EVENTCHECK\, GLOBAL(\RST~dataout\), , , , )

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	packed_mode => "false",
	lut_mask => "F303",
	clock_enable_mode => "false",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	datab => \inst|add_rtl_5|adder|result_node|cs_buffer[1]\,
	datac => \FreDec~dataout\,
	datad => \inst|add_rtl_4|adder|result_node|cs_buffer[1]\,
	aclr => \ALT_INV_RST~dataout\,
	clk => \inst|EVENTCHECK\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \inst|PASTEP[7]\);

\inst|add_rtl_5|adder|result_node|cs_buffer[2]~I\ : flex10ke_lcell
-- Equation(s):
-- \inst|add_rtl_5|adder|result_node|cs_buffer[2]\ = \inst|PASTEP[8]\ $ \inst|add_rtl_5|adder|result_node|cout[1]\
-- \inst|add_rtl_5|adder|result_node|cout[2]\ = CARRY(\inst|PASTEP[8]\ # \inst|add_rtl_5|adder|result_node|cout[1]\)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "arithmetic",
	cin_used => "true",
	packed_mode => "false",
	lut_mask => "3CFC",
	clock_enable_mode => "false",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	datab => \inst|PASTEP[8]\,
	cin => \inst|add_rtl_5|adder|result_node|cout[1]\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \inst|add_rtl_5|adder|result_node|cs_buffer[2]\,
	cout => \inst|add_rtl_5|adder|result_node|cout[2]\);

\inst|add_rtl_4|adder|result_node|cs_buffer[2]~I\ : flex10ke_lcell
-- Equation(s):
-- \inst|add_rtl_4|adder|result_node|cs_buffer[2]\ = \inst|PASTEP[8]\ $ \inst|add_rtl_4|adder|result_node|cout[1]\
-- \inst|add_rtl_4|adder|result_node|cout[2]\ = CARRY(\inst|PASTEP[8]\ & \inst|add_rtl_4|adder|result_node|cout[1]\)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "arithmetic",
	cin_used => "true",
	packed_mode => "false",
	lut_mask => "3CC0",
	clock_enable_mode => "false",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	datab => \inst|PASTEP[8]\,
	cin => \inst|add_rtl_4|adder|result_node|cout[1]\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \inst|add_rtl_4|adder|result_node|cs_buffer[2]\,
	cout => \inst|add_rtl_4|adder|result_node|cout[2]\);

\inst|PASTEP[8]~I\ : flex10ke_lcell
-- Equation(s):
-- \inst|PASTEP[8]\ = DFFEA(\FreDec~dataout\ & (\inst|add_rtl_4|adder|result_node|cs_buffer[2]\) # !\FreDec~dataout\ & !\inst|add_rtl_5|adder|result_node|cs_buffer[2]\, \inst|EVENTCHECK\, GLOBAL(\RST~dataout\), , , , )

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	packed_mode => "false",
	lut_mask => "F303",
	clock_enable_mode => "false",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	datab => \inst|add_rtl_5|adder|result_node|cs_buffer[2]\,
	datac => \FreDec~dataout\,
	datad => \inst|add_rtl_4|adder|result_node|cs_buffer[2]\,
	aclr => \ALT_INV_RST~dataout\,
	clk => \inst|EVENTCHECK\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \inst|PASTEP[8]\);

\inst|add_rtl_5|adder|result_node|cs_buffer[3]~I\ : flex10ke_lcell
-- Equation(s):
-- \inst|add_rtl_5|adder|result_node|cs_buffer[3]\ = \inst|PASTEP[9]\ $ \inst|add_rtl_5|adder|result_node|cout[2]\
-- \inst|add_rtl_5|adder|result_node|cout[3]\ = CARRY(\inst|PASTEP[9]\ # \inst|add_rtl_5|adder|result_node|cout[2]\)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "arithmetic",
	cin_used => "true",
	packed_mode => "false",
	lut_mask => "3CFC",
	clock_enable_mode => "false",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	datab => \inst|PASTEP[9]\,
	cin => \inst|add_rtl_5|adder|result_node|cout[2]\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \inst|add_rtl_5|adder|result_node|cs_buffer[3]\,
	cout => \inst|add_rtl_5|adder|result_node|cout[3]\);

\inst|add_rtl_4|adder|result_node|cs_buffer[3]~I\ : flex10ke_lcell
-- Equation(s):
-- \inst|add_rtl_4|adder|result_node|cs_buffer[3]\ = \inst|PASTEP[9]\ $ \inst|add_rtl_4|adder|result_node|cout[2]\
-- \inst|add_rtl_4|adder|result_node|cout[3]\ = CARRY(\inst|PASTEP[9]\ & \inst|add_rtl_4|adder|result_node|cout[2]\)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "arithmetic",
	cin_used => "true",
	packed_mode => "false",
	lut_mask => "3CC0",
	clock_enable_mode => "false",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	datab => \inst|PASTEP[9]\,
	cin => \inst|add_rtl_4|adder|result_node|cout[2]\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \inst|add_rtl_4|adder|result_node|cs_buffer[3]\,
	cout => \inst|add_rtl_4|adder|result_node|cout[3]\);

\inst|PASTEP[9]~I\ : flex10ke_lcell
-- Equation(s):
-- \inst|PASTEP[9]\ = DFFEA(\FreDec~dataout\ & (\inst|add_rtl_4|adder|result_node|cs_buffer[3]\) # !\FreDec~dataout\ & !\inst|add_rtl_5|adder|result_node|cs_buffer[3]\, \inst|EVENTCHECK\, GLOBAL(\RST~dataout\), , , , )

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	packed_mode => "false",
	lut_mask => "F303",
	clock_enable_mode => "false",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	datab => \inst|add_rtl_5|adder|result_node|cs_buffer[3]\,
	datac => \FreDec~dataout\,
	datad => \inst|add_rtl_4|adder|result_node|cs_buffer[3]\,
	aclr => \ALT_INV_RST~dataout\,
	clk => \inst|EVENTCHECK\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \inst|PASTEP[9]\);

\inst|add_rtl_5|adder|result_node|cs_buffer[4]~I\ : flex10ke_lcell
-- Equation(s):
-- \inst|add_rtl_5|adder|result_node|cs_buffer[4]\ = \inst|PASTEP[10]\ $ \inst|add_rtl_5|adder|result_node|cout[3]\
-- \inst|add_rtl_5|adder|result_node|cout[4]\ = CARRY(\inst|PASTEP[10]\ # \inst|add_rtl_5|adder|result_node|cout[3]\)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "arithmetic",
	cin_used => "true",
	packed_mode => "false",
	lut_mask => "3CFC",
	clock_enable_mode => "false",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	datab => \inst|PASTEP[10]\,
	cin => \inst|add_rtl_5|adder|result_node|cout[3]\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \inst|add_rtl_5|adder|result_node|cs_buffer[4]\,
	cout => \inst|add_rtl_5|adder|result_node|cout[4]\);

\inst|add_rtl_4|adder|result_node|cs_buffer[4]~I\ : flex10ke_lcell
-- Equation(s):
-- \inst|add_rtl_4|adder|result_node|cs_buffer[4]\ = \inst|PASTEP[10]\ $ \inst|add_rtl_4|adder|result_node|cout[3]\
-- \inst|add_rtl_4|adder|result_node|cout[4]\ = CARRY(\inst|PASTEP[10]\ & \inst|add_rtl_4|adder|result_node|cout[3]\)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "arithmetic",
	cin_used => "true",
	packed_mode => "false",
	lut_mask => "3CC0",
	clock_enable_mode => "false",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	datab => \inst|PASTEP[10]\,
	cin => \inst|add_rtl_4|adder|result_node|cout[3]\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \inst|add_rtl_4|adder|result_node|cs_buffer[4]\,
	cout => \inst|add_rtl_4|adder|result_node|cout[4]\);

\inst|PASTEP[10]~I\ : flex10ke_lcell
-- Equation(s):
-- \inst|PASTEP[10]\ = DFFEA(\FreDec~dataout\ & (\inst|add_rtl_4|adder|result_node|cs_buffer[4]\) # !\FreDec~dataout\ & !\inst|add_rtl_5|adder|result_node|cs_buffer[4]\, \inst|EVENTCHECK\, GLOBAL(\RST~dataout\), , , , )

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	packed_mode => "false",
	lut_mask => "F303",
	clock_enable_mode => "false",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	datab => \inst|add_rtl_5|adder|result_node|cs_buffer[4]\,
	datac => \FreDec~dataout\,
	datad => \inst|add_rtl_4|adder|result_node|cs_buffer[4]\,
	aclr => \ALT_INV_RST~dataout\,
	clk => \inst|EVENTCHECK\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \inst|PASTEP[10]\);

\inst|add_rtl_5|adder|result_node|cs_buffer[5]~I\ : flex10ke_lcell
-- Equation(s):
-- \inst|add_rtl_5|adder|result_node|cs_buffer[5]\ = \inst|PASTEP[11]\ $ \inst|add_rtl_5|adder|result_node|cout[4]\
-- \inst|add_rtl_5|adder|result_node|cout[5]\ = CARRY(\inst|PASTEP[11]\ # \inst|add_rtl_5|adder|result_node|cout[4]\)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "arithmetic",
	cin_used => "true",
	packed_mode => "false",
	lut_mask => "3CFC",
	clock_enable_mode => "false",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	datab => \inst|PASTEP[11]\,
	cin => \inst|add_rtl_5|adder|result_node|cout[4]\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \inst|add_rtl_5|adder|result_node|cs_buffer[5]\,
	cout => \inst|add_rtl_5|adder|result_node|cout[5]\);

\inst|add_rtl_4|adder|result_node|cs_buffer[5]~I\ : flex10ke_lcell
-- Equation(s):
-- \inst|add_rtl_4|adder|result_node|cs_buffer[5]\ = \inst|PASTEP[11]\ $ \inst|add_rtl_4|adder|result_node|cout[4]\
-- \inst|add_rtl_4|adder|result_node|cout[5]\ = CARRY(\inst|PASTEP[11]\ & \inst|add_rtl_4|adder|result_node|cout[4]\)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "arithmetic",
	cin_used => "true",
	packed_mode => "false",
	lut_mask => "3CC0",
	clock_enable_mode => "false",
	output_mode =>
上一页 1 2 3 45
💿 文件大小 509 K
👤 上传用户 shicg666666
📂 所属分类单片机开发
🏷️ 相关标签

#FPGA #资源 #任意波形
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