dds.vho

来自「利用FPGA的资源实现任意波形的产生」· VHO 代码 · 共 1,445 行 · 第 1/5 页

VHO
1,445 行
字号
12345
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	datad => \inst|add_rtl_3|adder|result_node|cs_buffer[3]\,
	aclr => \ALT_INV_RST~dataout\,
	clk => \inst|ALT_INV_FP2\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \inst|PAREG[9]\);

\inst|add_rtl_3|adder|result_node|cs_buffer[2]~I\ : flex10ke_lcell
-- Equation(s):
-- \inst|add_rtl_3|adder|result_node|cs_buffer[2]\ = \inst|PAREG[8]\ $ \inst|PASTEP[8]\ $ \inst|add_rtl_3|adder|result_node|cout[1]\
-- \inst|add_rtl_3|adder|result_node|cout[2]\ = CARRY(\inst|PAREG[8]\ & (\inst|PASTEP[8]\ # \inst|add_rtl_3|adder|result_node|cout[1]\) # !\inst|PAREG[8]\ & \inst|PASTEP[8]\ & \inst|add_rtl_3|adder|result_node|cout[1]\)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "arithmetic",
	cin_used => "true",
	packed_mode => "false",
	lut_mask => "96E8",
	clock_enable_mode => "false",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	dataa => \inst|PAREG[8]\,
	datab => \inst|PASTEP[8]\,
	cin => \inst|add_rtl_3|adder|result_node|cout[1]\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \inst|add_rtl_3|adder|result_node|cs_buffer[2]\,
	cout => \inst|add_rtl_3|adder|result_node|cout[2]\);

\inst|PAREG[8]~I\ : flex10ke_lcell
-- Equation(s):
-- \inst|PAREG[8]\ = DFFEA(\inst|add_rtl_3|adder|result_node|cs_buffer[2]\, !GLOBAL(\inst|FP2\), GLOBAL(\RST~dataout\), , , , )

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	packed_mode => "false",
	lut_mask => "FF00",
	clock_enable_mode => "false",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	datad => \inst|add_rtl_3|adder|result_node|cs_buffer[2]\,
	aclr => \ALT_INV_RST~dataout\,
	clk => \inst|ALT_INV_FP2\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \inst|PAREG[8]\);

\inst|add_rtl_3|adder|result_node|cs_buffer[1]~I\ : flex10ke_lcell
-- Equation(s):
-- \inst|add_rtl_3|adder|result_node|cs_buffer[1]\ = \inst|PAREG[7]\ $ \inst|PASTEP[7]\ $ \inst|add_rtl_3|adder|result_node|cout[0]\
-- \inst|add_rtl_3|adder|result_node|cout[1]\ = CARRY(\inst|PAREG[7]\ & (\inst|PASTEP[7]\ # \inst|add_rtl_3|adder|result_node|cout[0]\) # !\inst|PAREG[7]\ & \inst|PASTEP[7]\ & \inst|add_rtl_3|adder|result_node|cout[0]\)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "arithmetic",
	cin_used => "true",
	packed_mode => "false",
	lut_mask => "96E8",
	clock_enable_mode => "false",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	dataa => \inst|PAREG[7]\,
	datab => \inst|PASTEP[7]\,
	cin => \inst|add_rtl_3|adder|result_node|cout[0]\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \inst|add_rtl_3|adder|result_node|cs_buffer[1]\,
	cout => \inst|add_rtl_3|adder|result_node|cout[1]\);

\inst|PAREG[7]~I\ : flex10ke_lcell
-- Equation(s):
-- \inst|PAREG[7]\ = DFFEA(\inst|add_rtl_3|adder|result_node|cs_buffer[1]\, !GLOBAL(\inst|FP2\), GLOBAL(\RST~dataout\), , , , )

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	packed_mode => "false",
	lut_mask => "FF00",
	clock_enable_mode => "false",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	datad => \inst|add_rtl_3|adder|result_node|cs_buffer[1]\,
	aclr => \ALT_INV_RST~dataout\,
	clk => \inst|ALT_INV_FP2\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \inst|PAREG[7]\);

\inst|PASTEP[6]~I\ : flex10ke_lcell
-- Equation(s):
-- \inst|PASTEP[6]\ = DFFEA((!\inst|PASTEP[6]\ & \inst|PASTEP[6]~371\) # (\inst|add_rtl_4|adder|result_node|cs_buffer[0]~222\ & !\inst|PASTEP[6]~371\), \inst|EVENTCHECK\, GLOBAL(\RST~dataout\), , , , )
-- \inst|add_rtl_5|adder|result_node|cout[0]\ = CARRY(\inst|PASTEP[6]\)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "up_dn_cntr",
	packed_mode => "false",
	lut_mask => "33AA",
	clock_enable_mode => "false",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	datac => \inst|add_rtl_4|adder|result_node|cs_buffer[0]~222\,
	datad => \inst|PASTEP[6]~371\,
	aclr => \ALT_INV_RST~dataout\,
	clk => \inst|EVENTCHECK\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \inst|PASTEP[6]\,
	cout => \inst|add_rtl_5|adder|result_node|cout[0]\);

\RST~I\ : flex10ke_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	reg_source_mode => "none",
	feedback_mode => "from_pin")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	ena => VCC,
	padio => ww_RST,
	dataout => \RST~dataout\);

\CLK~I\ : flex10ke_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	reg_source_mode => "none",
	feedback_mode => "from_pin")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	ena => VCC,
	padio => ww_CLK,
	dataout => \CLK~dataout\);

\inst|FP2~I\ : flex10ke_lcell
-- Equation(s):
-- \inst|FP2\ = DFFEA(!\inst|FP2\, !GLOBAL(\CLK~dataout\), GLOBAL(\RST~dataout\), , , , )

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	packed_mode => "false",
	lut_mask => "00FF",
	clock_enable_mode => "false",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	datad => \inst|FP2\,
	aclr => \ALT_INV_RST~dataout\,
	clk => \ALT_INV_CLK~dataout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \inst|FP2\);

\FreInc~I\ : flex10ke_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	reg_source_mode => "none",
	feedback_mode => "from_pin")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	ena => VCC,
	padio => ww_FreInc,
	dataout => \FreInc~dataout\);

\inst|add_rtl_4|adder|result_node|cs_buffer[0]~I\ : flex10ke_lcell
-- Equation(s):
-- \inst|add_rtl_4|adder|result_node|cs_buffer[0]\ = \inst|PASTEP[6]\ $ \FreInc~dataout\
-- \inst|add_rtl_4|adder|result_node|cout[0]\ = CARRY(\inst|PASTEP[6]\ & !\FreInc~dataout\)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "arithmetic",
	packed_mode => "false",
	lut_mask => "6622",
	clock_enable_mode => "false",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	dataa => \inst|PASTEP[6]\,
	datab => \FreInc~dataout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \inst|add_rtl_4|adder|result_node|cs_buffer[0]\,
	cout => \inst|add_rtl_4|adder|result_node|cout[0]\);

\inst|add_rtl_4|adder|result_node|cs_buffer[0]~222_I\ : flex10ke_lcell
-- Equation(s):
-- \inst|add_rtl_4|adder|result_node|cs_buffer[0]~222\ = !\inst|add_rtl_4|adder|result_node|cs_buffer[0]\

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	packed_mode => "false",
	lut_mask => "00FF",
	clock_enable_mode => "false",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	datad => \inst|add_rtl_4|adder|result_node|cs_buffer[0]\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \inst|add_rtl_4|adder|result_node|cs_buffer[0]~222\);

\FreDec~I\ : flex10ke_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	reg_source_mode => "none",
	feedback_mode => "from_pin")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	ena => VCC,
	padio => ww_FreDec,
	dataout => \FreDec~dataout\);

\inst|PASTEP[6]~371_I\ : flex10ke_lcell
-- Equation(s):
-- \inst|PASTEP[6]~371\ = !\FreDec~dataout\

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	packed_mode => "false",
	lut_mask => "00FF",
	clock_enable_mode => "false",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	datad => \FreDec~dataout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \inst|PASTEP[6]~371\);

\inst|EVENTCHECK~I\ : flex10ke_lcell
-- Equation(s):
-- \inst|EVENTCHECK\ = !\FreDec~dataout\ # !\FreInc~dataout\

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	packed_mode => "false",
	lut_mask => "0FFF",
	clock_enable_mode => "false",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	datac => \FreInc~dataout\,
	datad => \FreDec~dataout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \inst|EVENTCHECK\);

\inst|add_rtl_5|adder|result_node|cs_buffer[1]~I\ : flex10ke_lcell
-- Equation(s):
-- \inst|add_rtl_5|adder|result_node|cs_buffer[1]\ = \inst|PASTEP[7]\ $ \inst|add_rtl_5|adder|result_node|cout[0]\
-- \inst|add_rtl_5|adder|result_node|cout[1]\ = CARRY(\inst|PASTEP[7]\ # \inst|add_rtl_5|adder|result_node|cout[0]\)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "arithmetic",
	cin_used => "true",
	packed_mode => "false",
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dds.vho - 源码说明

本页面展示了「利用FPGA的资源实现任意波形的产生」中的 dds.vho 源码文件，采用 VHO 编程语言编写，共 1,445 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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