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📁 利用FPGA的资源实现任意波形的产生
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-- \inst|add_rtl_3|adder|result_node|cs_buffer[9]\ = \inst|PAREG[15]\ $ \inst|PASTEP[15]\ $ \inst|add_rtl_3|adder|result_node|cout[8]\
-- \inst|add_rtl_3|adder|result_node|cout[9]\ = CARRY(\inst|PAREG[15]\ & (\inst|PASTEP[15]\ # \inst|add_rtl_3|adder|result_node|cout[8]\) # !\inst|PAREG[15]\ & \inst|PASTEP[15]\ & \inst|add_rtl_3|adder|result_node|cout[8]\)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "arithmetic",
	cin_used => "true",
	packed_mode => "false",
	lut_mask => "96E8",
	clock_enable_mode => "false",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	dataa => \inst|PAREG[15]\,
	datab => \inst|PASTEP[15]\,
	cin => \inst|add_rtl_3|adder|result_node|cout[8]\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \inst|add_rtl_3|adder|result_node|cs_buffer[9]\,
	cout => \inst|add_rtl_3|adder|result_node|cout[9]\);

\inst|PAREG[15]~I\ : flex10ke_lcell
-- Equation(s):
-- \inst|PAREG[15]\ = DFFEA(\inst|add_rtl_3|adder|result_node|cs_buffer[9]\, !GLOBAL(\inst|FP2\), GLOBAL(\RST~dataout\), , , , )

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	packed_mode => "false",
	lut_mask => "FF00",
	clock_enable_mode => "false",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	datad => \inst|add_rtl_3|adder|result_node|cs_buffer[9]\,
	aclr => \ALT_INV_RST~dataout\,
	clk => \inst|ALT_INV_FP2\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \inst|PAREG[15]\);

\inst|add_rtl_3|adder|result_node|cs_buffer[8]~I\ : flex10ke_lcell
-- Equation(s):
-- \inst|add_rtl_3|adder|result_node|cs_buffer[8]\ = \inst|PAREG[14]\ $ \inst|PASTEP[14]\ $ \inst|add_rtl_3|adder|result_node|cout[7]\
-- \inst|add_rtl_3|adder|result_node|cout[8]\ = CARRY(\inst|PAREG[14]\ & (\inst|PASTEP[14]\ # \inst|add_rtl_3|adder|result_node|cout[7]\) # !\inst|PAREG[14]\ & \inst|PASTEP[14]\ & \inst|add_rtl_3|adder|result_node|cout[7]\)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "arithmetic",
	cin_used => "true",
	packed_mode => "false",
	lut_mask => "96E8",
	clock_enable_mode => "false",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	dataa => \inst|PAREG[14]\,
	datab => \inst|PASTEP[14]\,
	cin => \inst|add_rtl_3|adder|result_node|cout[7]\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \inst|add_rtl_3|adder|result_node|cs_buffer[8]\,
	cout => \inst|add_rtl_3|adder|result_node|cout[8]\);

\inst|PAREG[14]~I\ : flex10ke_lcell
-- Equation(s):
-- \inst|PAREG[14]\ = DFFEA(\inst|add_rtl_3|adder|result_node|cs_buffer[8]\, !GLOBAL(\inst|FP2\), GLOBAL(\RST~dataout\), , , , )

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	packed_mode => "false",
	lut_mask => "FF00",
	clock_enable_mode => "false",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	datad => \inst|add_rtl_3|adder|result_node|cs_buffer[8]\,
	aclr => \ALT_INV_RST~dataout\,
	clk => \inst|ALT_INV_FP2\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \inst|PAREG[14]\);

\inst|add_rtl_3|adder|result_node|cs_buffer[7]~I\ : flex10ke_lcell
-- Equation(s):
-- \inst|add_rtl_3|adder|result_node|cs_buffer[7]\ = \inst|PAREG[13]\ $ \inst|PASTEP[13]\ $ \inst|add_rtl_3|adder|result_node|cout[6]\
-- \inst|add_rtl_3|adder|result_node|cout[7]\ = CARRY(\inst|PAREG[13]\ & (\inst|PASTEP[13]\ # \inst|add_rtl_3|adder|result_node|cout[6]\) # !\inst|PAREG[13]\ & \inst|PASTEP[13]\ & \inst|add_rtl_3|adder|result_node|cout[6]\)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "arithmetic",
	cin_used => "true",
	packed_mode => "false",
	lut_mask => "96E8",
	clock_enable_mode => "false",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	dataa => \inst|PAREG[13]\,
	datab => \inst|PASTEP[13]\,
	cin => \inst|add_rtl_3|adder|result_node|cout[6]\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \inst|add_rtl_3|adder|result_node|cs_buffer[7]\,
	cout => \inst|add_rtl_3|adder|result_node|cout[7]\);

\inst|PAREG[13]~I\ : flex10ke_lcell
-- Equation(s):
-- \inst|PAREG[13]\ = DFFEA(\inst|add_rtl_3|adder|result_node|cs_buffer[7]\, !GLOBAL(\inst|FP2\), GLOBAL(\RST~dataout\), , , , )

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	packed_mode => "false",
	lut_mask => "FF00",
	clock_enable_mode => "false",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	datad => \inst|add_rtl_3|adder|result_node|cs_buffer[7]\,
	aclr => \ALT_INV_RST~dataout\,
	clk => \inst|ALT_INV_FP2\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \inst|PAREG[13]\);

\inst|add_rtl_3|adder|result_node|cs_buffer[6]~I\ : flex10ke_lcell
-- Equation(s):
-- \inst|add_rtl_3|adder|result_node|cs_buffer[6]\ = \inst|PAREG[12]\ $ \inst|PASTEP[12]\ $ \inst|add_rtl_3|adder|result_node|cout[5]\
-- \inst|add_rtl_3|adder|result_node|cout[6]\ = CARRY(\inst|PAREG[12]\ & (\inst|PASTEP[12]\ # \inst|add_rtl_3|adder|result_node|cout[5]\) # !\inst|PAREG[12]\ & \inst|PASTEP[12]\ & \inst|add_rtl_3|adder|result_node|cout[5]\)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "arithmetic",
	cin_used => "true",
	packed_mode => "false",
	lut_mask => "96E8",
	clock_enable_mode => "false",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	dataa => \inst|PAREG[12]\,
	datab => \inst|PASTEP[12]\,
	cin => \inst|add_rtl_3|adder|result_node|cout[5]\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \inst|add_rtl_3|adder|result_node|cs_buffer[6]\,
	cout => \inst|add_rtl_3|adder|result_node|cout[6]\);

\inst|PAREG[12]~I\ : flex10ke_lcell
-- Equation(s):
-- \inst|PAREG[12]\ = DFFEA(\inst|add_rtl_3|adder|result_node|cs_buffer[6]\, !GLOBAL(\inst|FP2\), GLOBAL(\RST~dataout\), , , , )

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	packed_mode => "false",
	lut_mask => "FF00",
	clock_enable_mode => "false",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	datad => \inst|add_rtl_3|adder|result_node|cs_buffer[6]\,
	aclr => \ALT_INV_RST~dataout\,
	clk => \inst|ALT_INV_FP2\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \inst|PAREG[12]\);

\inst|add_rtl_3|adder|result_node|cs_buffer[5]~I\ : flex10ke_lcell
-- Equation(s):
-- \inst|add_rtl_3|adder|result_node|cs_buffer[5]\ = \inst|PAREG[11]\ $ \inst|PASTEP[11]\ $ \inst|add_rtl_3|adder|result_node|cout[4]\
-- \inst|add_rtl_3|adder|result_node|cout[5]\ = CARRY(\inst|PAREG[11]\ & (\inst|PASTEP[11]\ # \inst|add_rtl_3|adder|result_node|cout[4]\) # !\inst|PAREG[11]\ & \inst|PASTEP[11]\ & \inst|add_rtl_3|adder|result_node|cout[4]\)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "arithmetic",
	cin_used => "true",
	packed_mode => "false",
	lut_mask => "96E8",
	clock_enable_mode => "false",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	dataa => \inst|PAREG[11]\,
	datab => \inst|PASTEP[11]\,
	cin => \inst|add_rtl_3|adder|result_node|cout[4]\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \inst|add_rtl_3|adder|result_node|cs_buffer[5]\,
	cout => \inst|add_rtl_3|adder|result_node|cout[5]\);

\inst|PAREG[11]~I\ : flex10ke_lcell
-- Equation(s):
-- \inst|PAREG[11]\ = DFFEA(\inst|add_rtl_3|adder|result_node|cs_buffer[5]\, !GLOBAL(\inst|FP2\), GLOBAL(\RST~dataout\), , , , )

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	packed_mode => "false",
	lut_mask => "FF00",
	clock_enable_mode => "false",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	datad => \inst|add_rtl_3|adder|result_node|cs_buffer[5]\,
	aclr => \ALT_INV_RST~dataout\,
	clk => \inst|ALT_INV_FP2\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \inst|PAREG[11]\);

\inst|add_rtl_3|adder|result_node|cs_buffer[4]~I\ : flex10ke_lcell
-- Equation(s):
-- \inst|add_rtl_3|adder|result_node|cs_buffer[4]\ = \inst|PAREG[10]\ $ \inst|PASTEP[10]\ $ \inst|add_rtl_3|adder|result_node|cout[3]\
-- \inst|add_rtl_3|adder|result_node|cout[4]\ = CARRY(\inst|PAREG[10]\ & (\inst|PASTEP[10]\ # \inst|add_rtl_3|adder|result_node|cout[3]\) # !\inst|PAREG[10]\ & \inst|PASTEP[10]\ & \inst|add_rtl_3|adder|result_node|cout[3]\)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "arithmetic",
	cin_used => "true",
	packed_mode => "false",
	lut_mask => "96E8",
	clock_enable_mode => "false",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	dataa => \inst|PAREG[10]\,
	datab => \inst|PASTEP[10]\,
	cin => \inst|add_rtl_3|adder|result_node|cout[3]\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \inst|add_rtl_3|adder|result_node|cs_buffer[4]\,
	cout => \inst|add_rtl_3|adder|result_node|cout[4]\);

\inst|PAREG[10]~I\ : flex10ke_lcell
-- Equation(s):
-- \inst|PAREG[10]\ = DFFEA(\inst|add_rtl_3|adder|result_node|cs_buffer[4]\, !GLOBAL(\inst|FP2\), GLOBAL(\RST~dataout\), , , , )

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	packed_mode => "false",
	lut_mask => "FF00",
	clock_enable_mode => "false",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	datad => \inst|add_rtl_3|adder|result_node|cs_buffer[4]\,
	aclr => \ALT_INV_RST~dataout\,
	clk => \inst|ALT_INV_FP2\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \inst|PAREG[10]\);

\inst|add_rtl_3|adder|result_node|cs_buffer[3]~I\ : flex10ke_lcell
-- Equation(s):
-- \inst|add_rtl_3|adder|result_node|cs_buffer[3]\ = \inst|PAREG[9]\ $ \inst|PASTEP[9]\ $ \inst|add_rtl_3|adder|result_node|cout[2]\
-- \inst|add_rtl_3|adder|result_node|cout[3]\ = CARRY(\inst|PAREG[9]\ & (\inst|PASTEP[9]\ # \inst|add_rtl_3|adder|result_node|cout[2]\) # !\inst|PAREG[9]\ & \inst|PASTEP[9]\ & \inst|add_rtl_3|adder|result_node|cout[2]\)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "arithmetic",
	cin_used => "true",
	packed_mode => "false",
	lut_mask => "96E8",
	clock_enable_mode => "false",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	dataa => \inst|PAREG[9]\,
	datab => \inst|PASTEP[9]\,
	cin => \inst|add_rtl_3|adder|result_node|cout[2]\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \inst|add_rtl_3|adder|result_node|cs_buffer[3]\,
	cout => \inst|add_rtl_3|adder|result_node|cout[3]\);

\inst|PAREG[9]~I\ : flex10ke_lcell
-- Equation(s):
-- \inst|PAREG[9]\ = DFFEA(\inst|add_rtl_3|adder|result_node|cs_buffer[3]\, !GLOBAL(\inst|FP2\), GLOBAL(\RST~dataout\), , , , )

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	packed_mode => "false",
	lut_mask => "FF00",
	clock_enable_mode => "false",
💿 文件大小 509 K
👤 上传用户 shicg666666
📂 所属分类单片机开发
🏷️ 相关标签

#FPGA #资源 #任意波形
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