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SIGNAL \inst3|lpm_rom_component|srom|q[1]\ : std_logic;
SIGNAL \inst5|sanjiaoreg[1]\ : std_logic;
SIGNAL \inst5|add_rtl_0|adder|result_node|cs_buffer[0]~145\ : std_logic;
SIGNAL \inst2|lpm_rom_component|srom|q[1]\ : std_logic;
SIGNAL \inst5|juchireg[1]\ : std_logic;
SIGNAL \inst1|lpm_rom_component|srom|q[1]\ : std_logic;
SIGNAL \inst5|sinreg[1]\ : std_logic;
SIGNAL \inst5|add_rtl_0|adder|result_node|cs_buffer[1]~135\ : std_logic;
SIGNAL \inst5|add_rtl_1|adder|result_node|cs_buffer[1]~167\ : std_logic;
SIGNAL \inst3|lpm_rom_component|srom|q[2]\ : std_logic;
SIGNAL \inst5|sanjiaoreg[2]\ : std_logic;
SIGNAL \inst5|add_rtl_0|adder|result_node|cs_buffer[1]~139\ : std_logic;
SIGNAL \inst2|lpm_rom_component|srom|q[2]\ : std_logic;
SIGNAL \inst5|juchireg[2]\ : std_logic;
SIGNAL \inst1|lpm_rom_component|srom|q[2]\ : std_logic;
SIGNAL \inst5|sinreg[2]\ : std_logic;
SIGNAL \inst5|add_rtl_0|adder|result_node|cs_buffer[2]~127\ : std_logic;
SIGNAL \inst5|add_rtl_1|adder|result_node|cs_buffer[2]~159\ : std_logic;
SIGNAL \inst3|lpm_rom_component|srom|q[3]\ : std_logic;
SIGNAL \inst5|sanjiaoreg[3]\ : std_logic;
SIGNAL \inst5|add_rtl_0|adder|result_node|cs_buffer[2]~131\ : std_logic;
SIGNAL \inst2|lpm_rom_component|srom|q[3]\ : std_logic;
SIGNAL \inst5|juchireg[3]\ : std_logic;
SIGNAL \inst1|lpm_rom_component|srom|q[3]\ : std_logic;
SIGNAL \inst5|sinreg[3]\ : std_logic;
SIGNAL \inst5|add_rtl_0|adder|result_node|cs_buffer[3]~119\ : std_logic;
SIGNAL \inst5|add_rtl_1|adder|result_node|cs_buffer[3]~151\ : std_logic;
SIGNAL \inst3|lpm_rom_component|srom|q[4]\ : std_logic;
SIGNAL \inst5|sanjiaoreg[4]\ : std_logic;
SIGNAL \inst5|add_rtl_0|adder|result_node|cs_buffer[3]~123\ : std_logic;
SIGNAL \inst2|lpm_rom_component|srom|q[4]\ : std_logic;
SIGNAL \inst5|juchireg[4]\ : std_logic;
SIGNAL \inst1|lpm_rom_component|srom|q[4]\ : std_logic;
SIGNAL \inst5|sinreg[4]\ : std_logic;
SIGNAL \inst5|add_rtl_0|adder|result_node|cs_buffer[4]~111\ : std_logic;
SIGNAL \inst5|add_rtl_1|adder|result_node|cs_buffer[4]~143\ : std_logic;
SIGNAL \inst3|lpm_rom_component|srom|q[5]\ : std_logic;
SIGNAL \inst5|sanjiaoreg[5]\ : std_logic;
SIGNAL \inst5|add_rtl_0|adder|result_node|cs_buffer[4]~115\ : std_logic;
SIGNAL \inst2|lpm_rom_component|srom|q[5]\ : std_logic;
SIGNAL \inst5|juchireg[5]\ : std_logic;
SIGNAL \inst1|lpm_rom_component|srom|q[5]\ : std_logic;
SIGNAL \inst5|sinreg[5]\ : std_logic;
SIGNAL \inst5|add_rtl_0|adder|result_node|cs_buffer[5]~103\ : std_logic;
SIGNAL \inst5|add_rtl_1|adder|result_node|cs_buffer[5]~135\ : std_logic;
SIGNAL \inst5|add_rtl_0|adder|result_node|cs_buffer[5]~107\ : std_logic;
SIGNAL \inst5|add_rtl_1|adder|result_node|cs_buffer[6]~127\ : std_logic;
SIGNAL \inst4|lpm_rom_component|srom|q[0]\ : std_logic;
SIGNAL \PathSel[3]~dataout\ : std_logic;
SIGNAL \inst5|fangboreg[0]\ : std_logic;
SIGNAL \inst5|add_rtl_1|adder|result_node|cs_buffer[0]~170\ : std_logic;
SIGNAL \inst5|add_rtl_2|adder|result_node|cs_buffer[1]~132\ : std_logic;
SIGNAL \inst4|lpm_rom_component|srom|q[1]\ : std_logic;
SIGNAL \inst5|fangboreg[1]\ : std_logic;
SIGNAL \inst5|add_rtl_1|adder|result_node|cs_buffer[1]~163\ : std_logic;
SIGNAL \inst5|add_rtl_2|adder|result_node|cs_buffer[2]~126\ : std_logic;
SIGNAL \inst4|lpm_rom_component|srom|q[2]\ : std_logic;
SIGNAL \inst5|fangboreg[2]\ : std_logic;
SIGNAL \inst5|add_rtl_1|adder|result_node|cs_buffer[2]~155\ : std_logic;
SIGNAL \inst5|add_rtl_2|adder|result_node|cs_buffer[3]~118\ : std_logic;
SIGNAL \inst4|lpm_rom_component|srom|q[3]\ : std_logic;
SIGNAL \inst5|fangboreg[3]\ : std_logic;
SIGNAL \inst5|add_rtl_1|adder|result_node|cs_buffer[3]~147\ : std_logic;
SIGNAL \inst5|add_rtl_2|adder|result_node|cs_buffer[4]~110\ : std_logic;
SIGNAL \inst4|lpm_rom_component|srom|q[4]\ : std_logic;
SIGNAL \inst5|fangboreg[4]\ : std_logic;
SIGNAL \inst5|add_rtl_1|adder|result_node|cs_buffer[4]~139\ : std_logic;
SIGNAL \inst5|add_rtl_2|adder|result_node|cs_buffer[5]~102\ : std_logic;
SIGNAL \inst4|lpm_rom_component|srom|q[5]\ : std_logic;
SIGNAL \inst5|fangboreg[5]\ : std_logic;
SIGNAL \inst5|add_rtl_1|adder|result_node|cs_buffer[5]~131\ : std_logic;
SIGNAL \inst5|add_rtl_2|adder|result_node|cs_buffer[6]~94\ : std_logic;
SIGNAL \inst5|add_rtl_1|adder|result_node|cs_buffer[6]~124\ : std_logic;
SIGNAL \inst5|add_rtl_2|adder|result_node|cs_buffer[7]~86\ : std_logic;
SIGNAL \inst5|add_rtl_2|adder|unreg_res_node[8]\ : std_logic;
SIGNAL \inst5|add_rtl_2|adder|result_node|cs_buffer[7]~83\ : std_logic;
SIGNAL \inst5|add_rtl_2|adder|result_node|cs_buffer[6]~90\ : std_logic;
SIGNAL \inst5|add_rtl_2|adder|result_node|cs_buffer[5]~98\ : std_logic;
SIGNAL \inst5|add_rtl_2|adder|result_node|cs_buffer[4]~106\ : std_logic;
SIGNAL \inst5|add_rtl_2|adder|result_node|cs_buffer[3]~114\ : std_logic;
SIGNAL \inst5|add_rtl_2|adder|result_node|cs_buffer[2]~122\ : std_logic;
SIGNAL \inst5|add_rtl_2|adder|result_node|cs_buffer[1]~129\ : std_logic;
SIGNAL \inst5|add_rtl_2|adder|ALT_INV_unreg_res_node[8]\ : std_logic;
SIGNAL \inst5|add_rtl_2|adder|result_node|ALT_INV_cs_buffer[1]~129\ : std_logic;
SIGNAL \inst|ALT_INV_FP2\ : std_logic;
SIGNAL \ALT_INV_CLK~dataout\ : std_logic;
SIGNAL \ALT_INV_RST~dataout\ : std_logic;
BEGIN
toda <= ww_toda;
ww_CLK <= CLK;
ww_RST <= RST;
ww_FreDec <= FreDec;
ww_FreInc <= FreInc;
ww_PathSel <= PathSel;
ww_devoe <= devoe;
ww_devclrn <= devclrn;
ww_devpor <= devpor;
\inst4|lpm_rom_component|srom|segment[0][5]_WADDR_bus\ <= (gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd);
\inst4|lpm_rom_component|srom|segment[0][5]_RADDR_bus\ <= (gnd & gnd & gnd & gnd & gnd & \inst|PAREG[23]\ & \inst|PAREG[22]\ & \inst|PAREG[21]\ & \inst|PAREG[20]\ & \inst|PAREG[19]\ & \inst|PAREG[18]\);
\inst4|lpm_rom_component|srom|segment[0][4]_WADDR_bus\ <= (gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd);
\inst4|lpm_rom_component|srom|segment[0][4]_RADDR_bus\ <= (gnd & gnd & gnd & gnd & gnd & \inst|PAREG[23]\ & \inst|PAREG[22]\ & \inst|PAREG[21]\ & \inst|PAREG[20]\ & \inst|PAREG[19]\ & \inst|PAREG[18]\);
\inst4|lpm_rom_component|srom|segment[0][3]_WADDR_bus\ <= (gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd);
\inst4|lpm_rom_component|srom|segment[0][3]_RADDR_bus\ <= (gnd & gnd & gnd & gnd & gnd & \inst|PAREG[23]\ & \inst|PAREG[22]\ & \inst|PAREG[21]\ & \inst|PAREG[20]\ & \inst|PAREG[19]\ & \inst|PAREG[18]\);
\inst4|lpm_rom_component|srom|segment[0][2]_WADDR_bus\ <= (gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd);
\inst4|lpm_rom_component|srom|segment[0][2]_RADDR_bus\ <= (gnd & gnd & gnd & gnd & gnd & \inst|PAREG[23]\ & \inst|PAREG[22]\ & \inst|PAREG[21]\ & \inst|PAREG[20]\ & \inst|PAREG[19]\ & \inst|PAREG[18]\);
\inst4|lpm_rom_component|srom|segment[0][1]_WADDR_bus\ <= (gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd);
\inst4|lpm_rom_component|srom|segment[0][1]_RADDR_bus\ <= (gnd & gnd & gnd & gnd & gnd & \inst|PAREG[23]\ & \inst|PAREG[22]\ & \inst|PAREG[21]\ & \inst|PAREG[20]\ & \inst|PAREG[19]\ & \inst|PAREG[18]\);
\inst4|lpm_rom_component|srom|segment[0][0]_WADDR_bus\ <= (gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd);
\inst4|lpm_rom_component|srom|segment[0][0]_RADDR_bus\ <= (gnd & gnd & gnd & gnd & gnd & \inst|PAREG[23]\ & \inst|PAREG[22]\ & \inst|PAREG[21]\ & \inst|PAREG[20]\ & \inst|PAREG[19]\ & \inst|PAREG[18]\);
\inst3|lpm_rom_component|srom|segment[0][5]_WADDR_bus\ <= (gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd);
\inst3|lpm_rom_component|srom|segment[0][5]_RADDR_bus\ <= (gnd & gnd & gnd & gnd & gnd & \inst|PAREG[23]\ & \inst|PAREG[22]\ & \inst|PAREG[21]\ & \inst|PAREG[20]\ & \inst|PAREG[19]\ & \inst|PAREG[18]\);
\inst3|lpm_rom_component|srom|segment[0][4]_WADDR_bus\ <= (gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd);
\inst3|lpm_rom_component|srom|segment[0][4]_RADDR_bus\ <= (gnd & gnd & gnd & gnd & gnd & \inst|PAREG[23]\ & \inst|PAREG[22]\ & \inst|PAREG[21]\ & \inst|PAREG[20]\ & \inst|PAREG[19]\ & \inst|PAREG[18]\);
\inst3|lpm_rom_component|srom|segment[0][3]_WADDR_bus\ <= (gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd);
\inst3|lpm_rom_component|srom|segment[0][3]_RADDR_bus\ <= (gnd & gnd & gnd & gnd & gnd & \inst|PAREG[23]\ & \inst|PAREG[22]\ & \inst|PAREG[21]\ & \inst|PAREG[20]\ & \inst|PAREG[19]\ & \inst|PAREG[18]\);
\inst3|lpm_rom_component|srom|segment[0][2]_WADDR_bus\ <= (gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd);
\inst3|lpm_rom_component|srom|segment[0][2]_RADDR_bus\ <= (gnd & gnd & gnd & gnd & gnd & \inst|PAREG[23]\ & \inst|PAREG[22]\ & \inst|PAREG[21]\ & \inst|PAREG[20]\ & \inst|PAREG[19]\ & \inst|PAREG[18]\);
\inst3|lpm_rom_component|srom|segment[0][1]_WADDR_bus\ <= (gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd);
\inst3|lpm_rom_component|srom|segment[0][1]_RADDR_bus\ <= (gnd & gnd & gnd & gnd & gnd & \inst|PAREG[23]\ & \inst|PAREG[22]\ & \inst|PAREG[21]\ & \inst|PAREG[20]\ & \inst|PAREG[19]\ & \inst|PAREG[18]\);
\inst3|lpm_rom_component|srom|segment[0][0]_WADDR_bus\ <= (gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd);
\inst3|lpm_rom_component|srom|segment[0][0]_RADDR_bus\ <= (gnd & gnd & gnd & gnd & gnd & \inst|PAREG[23]\ & \inst|PAREG[22]\ & \inst|PAREG[21]\ & \inst|PAREG[20]\ & \inst|PAREG[19]\ & \inst|PAREG[18]\);
\inst1|lpm_rom_component|srom|segment[0][5]_WADDR_bus\ <= (gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd);
\inst1|lpm_rom_component|srom|segment[0][5]_RADDR_bus\ <= (gnd & gnd & gnd & gnd & gnd & \inst|PAREG[23]\ & \inst|PAREG[22]\ & \inst|PAREG[21]\ & \inst|PAREG[20]\ & \inst|PAREG[19]\ & \inst|PAREG[18]\);
\inst2|lpm_rom_component|srom|segment[0][5]_WADDR_bus\ <= (gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd);
\inst2|lpm_rom_component|srom|segment[0][5]_RADDR_bus\ <= (gnd & gnd & gnd & gnd & gnd & \inst|PAREG[23]\ & \inst|PAREG[22]\ & \inst|PAREG[21]\ & \inst|PAREG[20]\ & \inst|PAREG[19]\ & \inst|PAREG[18]\);
\inst1|lpm_rom_component|srom|segment[0][4]_WADDR_bus\ <= (gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd);
\inst1|lpm_rom_component|srom|segment[0][4]_RADDR_bus\ <= (gnd & gnd & gnd & gnd & gnd & \inst|PAREG[23]\ & \inst|PAREG[22]\ & \inst|PAREG[21]\ & \inst|PAREG[20]\ & \inst|PAREG[19]\ & \inst|PAREG[18]\);
\inst2|lpm_rom_component|srom|segment[0][4]_WADDR_bus\ <= (gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd);
\inst2|lpm_rom_component|srom|segment[0][4]_RADDR_bus\ <= (gnd & gnd & gnd & gnd & gnd & \inst|PAREG[23]\ & \inst|PAREG[22]\ & \inst|PAREG[21]\ & \inst|PAREG[20]\ & \inst|PAREG[19]\ & \inst|PAREG[18]\);
\inst1|lpm_rom_component|srom|segment[0][3]_WADDR_bus\ <= (gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd);
\inst1|lpm_rom_component|srom|segment[0][3]_RADDR_bus\ <= (gnd & gnd & gnd & gnd & gnd & \inst|PAREG[23]\ & \inst|PAREG[22]\ & \inst|PAREG[21]\ & \inst|PAREG[20]\ & \inst|PAREG[19]\ & \inst|PAREG[18]\);
\inst2|lpm_rom_component|srom|segment[0][3]_WADDR_bus\ <= (gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd);
\inst2|lpm_rom_component|srom|segment[0][3]_RADDR_bus\ <= (gnd & gnd & gnd & gnd & gnd & \inst|PAREG[23]\ & \inst|PAREG[22]\ & \inst|PAREG[21]\ & \inst|PAREG[20]\ & \inst|PAREG[19]\ & \inst|PAREG[18]\);
\inst1|lpm_rom_component|srom|segment[0][2]_WADDR_bus\ <= (gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd);
\inst1|lpm_rom_component|srom|segment[0][2]_RADDR_bus\ <= (gnd & gnd & gnd & gnd & gnd & \inst|PAREG[23]\ & \inst|PAREG[22]\ & \inst|PAREG[21]\ & \inst|PAREG[20]\ & \inst|PAREG[19]\ & \inst|PAREG[18]\);
\inst2|lpm_rom_component|srom|segment[0][2]_WADDR_bus\ <= (gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd);
\inst2|lpm_rom_component|srom|segment[0][2]_RADDR_bus\ <= (gnd & gnd & gnd & gnd & gnd & \inst|PAREG[23]\ & \inst|PAREG[22]\ & \inst|PAREG[21]\ & \inst|PAREG[20]\ & \inst|PAREG[19]\ & \inst|PAREG[18]\);
\inst1|lpm_rom_component|srom|segment[0][1]_WADDR_bus\ <= (gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd);
\inst1|lpm_rom_component|srom|segment[0][1]_RADDR_bus\ <= (gnd & gnd & gnd & gnd & gnd & \inst|PAREG[23]\ & \inst|PAREG[22]\ & \inst|PAREG[21]\ & \inst|PAREG[20]\ & \inst|PAREG[19]\ & \inst|PAREG[18]\);
\inst2|lpm_rom_component|srom|segment[0][1]_WADDR_bus\ <= (gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd);
\inst2|lpm_rom_component|srom|segment[0][1]_RADDR_bus\ <= (gnd & gnd & gnd & gnd & gnd & \inst|PAREG[23]\ & \inst|PAREG[22]\ & \inst|PAREG[21]\ & \inst|PAREG[20]\ & \inst|PAREG[19]\ & \inst|PAREG[18]\);
\inst2|lpm_rom_component|srom|segment[0][0]_WADDR_bus\ <= (gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd);
\inst2|lpm_rom_component|srom|segment[0][0]_RADDR_bus\ <= (gnd & gnd & gnd & gnd & gnd & \inst|PAREG[23]\ & \inst|PAREG[22]\ & \inst|PAREG[21]\ & \inst|PAREG[20]\ & \inst|PAREG[19]\ & \inst|PAREG[18]\);
\inst1|lpm_rom_component|srom|segment[0][0]_WADDR_bus\ <= (gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd);
\inst1|lpm_rom_component|srom|segment[0][0]_RADDR_bus\ <= (gnd & gnd & gnd & gnd & gnd & \inst|PAREG[23]\ & \inst|PAREG[22]\ & \inst|PAREG[21]\ & \inst|PAREG[20]\ & \inst|PAREG[19]\ & \inst|PAREG[18]\);
\inst5|add_rtl_2|adder|ALT_INV_unreg_res_node[8]\ <= NOT \inst5|add_rtl_2|adder|unreg_res_node[8]\;
\inst5|add_rtl_2|adder|result_node|ALT_INV_cs_buffer[1]~129\ <= NOT \inst5|add_rtl_2|adder|result_node|cs_buffer[1]~129\;
\inst|ALT_INV_FP2\ <= NOT \inst|FP2\;
\ALT_INV_CLK~dataout\ <= NOT \CLK~dataout\;
\ALT_INV_RST~dataout\ <= NOT \RST~dataout\;
\inst|add_rtl_3|adder|result_node|cs_buffer[11]~I\ : flex10ke_lcell
-- Equation(s):
-- \inst|add_rtl_3|adder|result_node|cs_buffer[11]\ = \inst|PAREG[17]\ $ \inst|PASTEP[17]\ $ \inst|add_rtl_3|adder|result_node|cout[10]\
-- \inst|add_rtl_3|adder|result_node|cout[11]\ = CARRY(\inst|PAREG[17]\ & (\inst|PASTEP[17]\ # \inst|add_rtl_3|adder|result_node|cout[10]\) # !\inst|PAREG[17]\ & \inst|PASTEP[17]\ & \inst|add_rtl_3|adder|result_node|cout[10]\)
-- pragma translate_off
GENERIC MAP (
operation_mode => "arithmetic",
cin_used => "true",
packed_mode => "false",
lut_mask => "96E8",
clock_enable_mode => "false",
output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
dataa => \inst|PAREG[17]\,
datab => \inst|PASTEP[17]\,
cin => \inst|add_rtl_3|adder|result_node|cout[10]\,
devclrn => ww_devclrn,
devpor => ww_devpor,
combout => \inst|add_rtl_3|adder|result_node|cs_buffer[11]\,
cout => \inst|add_rtl_3|adder|result_node|cout[11]\);
\inst|PAREG[17]~I\ : flex10ke_lcell
-- Equation(s):
-- \inst|PAREG[17]\ = DFFEA(\inst|add_rtl_3|adder|result_node|cs_buffer[11]\, !GLOBAL(\inst|FP2\), GLOBAL(\RST~dataout\), , , , )
-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
packed_mode => "false",
lut_mask => "FF00",
clock_enable_mode => "false",
output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
datad => \inst|add_rtl_3|adder|result_node|cs_buffer[11]\,
aclr => \ALT_INV_RST~dataout\,
clk => \inst|ALT_INV_FP2\,
devclrn => ww_devclrn,
devpor => ww_devpor,
regout => \inst|PAREG[17]\);
\inst|add_rtl_3|adder|result_node|cs_buffer[10]~I\ : flex10ke_lcell
-- Equation(s):
-- \inst|add_rtl_3|adder|result_node|cs_buffer[10]\ = \inst|PAREG[16]\ $ \inst|PASTEP[16]\ $ \inst|add_rtl_3|adder|result_node|cout[9]\
-- \inst|add_rtl_3|adder|result_node|cout[10]\ = CARRY(\inst|PAREG[16]\ & (\inst|PASTEP[16]\ # \inst|add_rtl_3|adder|result_node|cout[9]\) # !\inst|PAREG[16]\ & \inst|PASTEP[16]\ & \inst|add_rtl_3|adder|result_node|cout[9]\)
-- pragma translate_off
GENERIC MAP (
operation_mode => "arithmetic",
cin_used => "true",
packed_mode => "false",
lut_mask => "96E8",
clock_enable_mode => "false",
output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
dataa => \inst|PAREG[16]\,
datab => \inst|PASTEP[16]\,
cin => \inst|add_rtl_3|adder|result_node|cout[9]\,
devclrn => ww_devclrn,
devpor => ww_devpor,
combout => \inst|add_rtl_3|adder|result_node|cs_buffer[10]\,
cout => \inst|add_rtl_3|adder|result_node|cout[10]\);
\inst|PAREG[16]~I\ : flex10ke_lcell
-- Equation(s):
-- \inst|PAREG[16]\ = DFFEA(\inst|add_rtl_3|adder|result_node|cs_buffer[10]\, !GLOBAL(\inst|FP2\), GLOBAL(\RST~dataout\), , , , )
-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
packed_mode => "false",
lut_mask => "FF00",
clock_enable_mode => "false",
output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
datad => \inst|add_rtl_3|adder|result_node|cs_buffer[10]\,
aclr => \ALT_INV_RST~dataout\,
clk => \inst|ALT_INV_FP2\,
devclrn => ww_devclrn,
devpor => ww_devpor,
regout => \inst|PAREG[16]\);
\inst|add_rtl_3|adder|result_node|cs_buffer[9]~I\ : flex10ke_lcell
-- Equation(s):
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