dds.vho

利用FPGA的资源实现任意波形的产生

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II"
-- VERSION "Version 5.1 Build 176 10/26/2005 SJ Full Version"

-- DATE "10/05/2006 13:49:20"

-- 
-- Device: Altera EP1K50TC144-1 Package TQFP144
-- 

-- 
-- This VHDL file should be used for ModelSim (VHDL) only
-- 

LIBRARY IEEE, flex10ke;
USE IEEE.std_logic_1164.all;
USE flex10ke.flex10ke_components.all;

ENTITY 	DDS IS
    PORT (
	toda : OUT std_logic_vector(7 DOWNTO 0);
	CLK : IN std_logic;
	RST : IN std_logic;
	FreDec : IN std_logic;
	FreInc : IN std_logic;
	PathSel : IN std_logic_vector(3 DOWNTO 0)
	);
END DDS;

ARCHITECTURE structure OF DDS IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL devoe : std_logic := '0';
SIGNAL devclrn : std_logic := '1';
SIGNAL devpor : std_logic := '1';
SIGNAL ww_devoe : std_logic;
SIGNAL ww_devclrn : std_logic;
SIGNAL ww_devpor : std_logic;
SIGNAL ww_toda : std_logic_vector(7 DOWNTO 0);
SIGNAL ww_CLK : std_logic;
SIGNAL ww_RST : std_logic;
SIGNAL ww_FreDec : std_logic;
SIGNAL ww_FreInc : std_logic;
SIGNAL ww_PathSel : std_logic_vector(3 DOWNTO 0);
SIGNAL \inst4|lpm_rom_component|srom|segment[0][5]_WADDR_bus\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst4|lpm_rom_component|srom|segment[0][5]_RADDR_bus\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst4|lpm_rom_component|srom|segment[0][4]_WADDR_bus\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst4|lpm_rom_component|srom|segment[0][4]_RADDR_bus\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst4|lpm_rom_component|srom|segment[0][3]_WADDR_bus\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst4|lpm_rom_component|srom|segment[0][3]_RADDR_bus\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst4|lpm_rom_component|srom|segment[0][2]_WADDR_bus\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst4|lpm_rom_component|srom|segment[0][2]_RADDR_bus\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst4|lpm_rom_component|srom|segment[0][1]_WADDR_bus\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst4|lpm_rom_component|srom|segment[0][1]_RADDR_bus\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst4|lpm_rom_component|srom|segment[0][0]_WADDR_bus\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst4|lpm_rom_component|srom|segment[0][0]_RADDR_bus\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst3|lpm_rom_component|srom|segment[0][5]_WADDR_bus\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst3|lpm_rom_component|srom|segment[0][5]_RADDR_bus\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst3|lpm_rom_component|srom|segment[0][4]_WADDR_bus\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst3|lpm_rom_component|srom|segment[0][4]_RADDR_bus\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst3|lpm_rom_component|srom|segment[0][3]_WADDR_bus\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst3|lpm_rom_component|srom|segment[0][3]_RADDR_bus\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst3|lpm_rom_component|srom|segment[0][2]_WADDR_bus\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst3|lpm_rom_component|srom|segment[0][2]_RADDR_bus\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst3|lpm_rom_component|srom|segment[0][1]_WADDR_bus\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst3|lpm_rom_component|srom|segment[0][1]_RADDR_bus\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst3|lpm_rom_component|srom|segment[0][0]_WADDR_bus\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst3|lpm_rom_component|srom|segment[0][0]_RADDR_bus\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst1|lpm_rom_component|srom|segment[0][5]_WADDR_bus\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst1|lpm_rom_component|srom|segment[0][5]_RADDR_bus\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst2|lpm_rom_component|srom|segment[0][5]_WADDR_bus\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst2|lpm_rom_component|srom|segment[0][5]_RADDR_bus\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst1|lpm_rom_component|srom|segment[0][4]_WADDR_bus\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst1|lpm_rom_component|srom|segment[0][4]_RADDR_bus\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst2|lpm_rom_component|srom|segment[0][4]_WADDR_bus\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst2|lpm_rom_component|srom|segment[0][4]_RADDR_bus\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst1|lpm_rom_component|srom|segment[0][3]_WADDR_bus\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst1|lpm_rom_component|srom|segment[0][3]_RADDR_bus\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst2|lpm_rom_component|srom|segment[0][3]_WADDR_bus\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst2|lpm_rom_component|srom|segment[0][3]_RADDR_bus\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst1|lpm_rom_component|srom|segment[0][2]_WADDR_bus\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst1|lpm_rom_component|srom|segment[0][2]_RADDR_bus\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst2|lpm_rom_component|srom|segment[0][2]_WADDR_bus\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst2|lpm_rom_component|srom|segment[0][2]_RADDR_bus\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst1|lpm_rom_component|srom|segment[0][1]_WADDR_bus\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst1|lpm_rom_component|srom|segment[0][1]_RADDR_bus\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst2|lpm_rom_component|srom|segment[0][1]_WADDR_bus\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst2|lpm_rom_component|srom|segment[0][1]_RADDR_bus\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst2|lpm_rom_component|srom|segment[0][0]_WADDR_bus\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst2|lpm_rom_component|srom|segment[0][0]_RADDR_bus\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst1|lpm_rom_component|srom|segment[0][0]_WADDR_bus\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst1|lpm_rom_component|srom|segment[0][0]_RADDR_bus\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst3|lpm_rom_component|srom|segment[0][0]_modesel\ : std_logic_vector(15 DOWNTO 0) := "0101000100010000";
SIGNAL \inst1|lpm_rom_component|srom|segment[0][0]_modesel\ : std_logic_vector(15 DOWNTO 0) := "0101000100010000";
SIGNAL \inst2|lpm_rom_component|srom|segment[0][0]_modesel\ : std_logic_vector(15 DOWNTO 0) := "0101000100010000";
SIGNAL \inst3|lpm_rom_component|srom|segment[0][1]_modesel\ : std_logic_vector(15 DOWNTO 0) := "0101000100010000";
SIGNAL \inst2|lpm_rom_component|srom|segment[0][1]_modesel\ : std_logic_vector(15 DOWNTO 0) := "0101000100010000";
SIGNAL \inst1|lpm_rom_component|srom|segment[0][1]_modesel\ : std_logic_vector(15 DOWNTO 0) := "0101000100010000";
SIGNAL \inst3|lpm_rom_component|srom|segment[0][2]_modesel\ : std_logic_vector(15 DOWNTO 0) := "0101000100010000";
SIGNAL \inst2|lpm_rom_component|srom|segment[0][2]_modesel\ : std_logic_vector(15 DOWNTO 0) := "0101000100010000";
SIGNAL \inst1|lpm_rom_component|srom|segment[0][2]_modesel\ : std_logic_vector(15 DOWNTO 0) := "0101000100010000";
SIGNAL \inst3|lpm_rom_component|srom|segment[0][3]_modesel\ : std_logic_vector(15 DOWNTO 0) := "0101000100010000";
SIGNAL \inst2|lpm_rom_component|srom|segment[0][3]_modesel\ : std_logic_vector(15 DOWNTO 0) := "0101000100010000";
SIGNAL \inst1|lpm_rom_component|srom|segment[0][3]_modesel\ : std_logic_vector(15 DOWNTO 0) := "0101000100010000";
SIGNAL \inst3|lpm_rom_component|srom|segment[0][4]_modesel\ : std_logic_vector(15 DOWNTO 0) := "0101000100010000";
SIGNAL \inst2|lpm_rom_component|srom|segment[0][4]_modesel\ : std_logic_vector(15 DOWNTO 0) := "0101000100010000";
SIGNAL \inst1|lpm_rom_component|srom|segment[0][4]_modesel\ : std_logic_vector(15 DOWNTO 0) := "0101000100010000";
SIGNAL \inst3|lpm_rom_component|srom|segment[0][5]_modesel\ : std_logic_vector(15 DOWNTO 0) := "0101000100010000";
SIGNAL \inst2|lpm_rom_component|srom|segment[0][5]_modesel\ : std_logic_vector(15 DOWNTO 0) := "0101000100010000";
SIGNAL \inst1|lpm_rom_component|srom|segment[0][5]_modesel\ : std_logic_vector(15 DOWNTO 0) := "0101000100010000";
SIGNAL \inst4|lpm_rom_component|srom|segment[0][0]_modesel\ : std_logic_vector(15 DOWNTO 0) := "0101000100010000";
SIGNAL \inst4|lpm_rom_component|srom|segment[0][1]_modesel\ : std_logic_vector(15 DOWNTO 0) := "0101000100010000";
SIGNAL \inst4|lpm_rom_component|srom|segment[0][2]_modesel\ : std_logic_vector(15 DOWNTO 0) := "0101000100010000";
SIGNAL \inst4|lpm_rom_component|srom|segment[0][3]_modesel\ : std_logic_vector(15 DOWNTO 0) := "0101000100010000";
SIGNAL \inst4|lpm_rom_component|srom|segment[0][4]_modesel\ : std_logic_vector(15 DOWNTO 0) := "0101000100010000";
SIGNAL \inst4|lpm_rom_component|srom|segment[0][5]_modesel\ : std_logic_vector(15 DOWNTO 0) := "0101000100010000";
SIGNAL \inst|add_rtl_3|adder|result_node|cs_buffer[11]\ : std_logic;
SIGNAL \inst|PAREG[17]\ : std_logic;
SIGNAL \inst|add_rtl_3|adder|result_node|cs_buffer[10]\ : std_logic;
SIGNAL \inst|PAREG[16]\ : std_logic;
SIGNAL \inst|add_rtl_3|adder|result_node|cs_buffer[9]\ : std_logic;
SIGNAL \inst|PAREG[15]\ : std_logic;
SIGNAL \inst|add_rtl_3|adder|result_node|cs_buffer[8]\ : std_logic;
SIGNAL \inst|PAREG[14]\ : std_logic;
SIGNAL \inst|add_rtl_3|adder|result_node|cs_buffer[7]\ : std_logic;
SIGNAL \inst|PAREG[13]\ : std_logic;
SIGNAL \inst|add_rtl_3|adder|result_node|cs_buffer[6]\ : std_logic;
SIGNAL \inst|PAREG[12]\ : std_logic;
SIGNAL \inst|add_rtl_3|adder|result_node|cs_buffer[5]\ : std_logic;
SIGNAL \inst|PAREG[11]\ : std_logic;
SIGNAL \inst|add_rtl_3|adder|result_node|cs_buffer[4]\ : std_logic;
SIGNAL \inst|PAREG[10]\ : std_logic;
SIGNAL \inst|add_rtl_3|adder|result_node|cs_buffer[3]\ : std_logic;
SIGNAL \inst|PAREG[9]\ : std_logic;
SIGNAL \inst|add_rtl_3|adder|result_node|cs_buffer[2]\ : std_logic;
SIGNAL \inst|PAREG[8]\ : std_logic;
SIGNAL \inst|add_rtl_3|adder|result_node|cs_buffer[1]\ : std_logic;
SIGNAL \inst|PAREG[7]\ : std_logic;
SIGNAL \inst|PASTEP[6]\ : std_logic;
SIGNAL \RST~dataout\ : std_logic;
SIGNAL \CLK~dataout\ : std_logic;
SIGNAL \inst|FP2\ : std_logic;
SIGNAL \FreInc~dataout\ : std_logic;
SIGNAL \inst|add_rtl_4|adder|result_node|cs_buffer[0]\ : std_logic;
SIGNAL \inst|add_rtl_4|adder|result_node|cs_buffer[0]~222\ : std_logic;
SIGNAL \FreDec~dataout\ : std_logic;
SIGNAL \inst|PASTEP[6]~371\ : std_logic;
SIGNAL \inst|EVENTCHECK\ : std_logic;
SIGNAL \inst|add_rtl_5|adder|result_node|cout[0]\ : std_logic;
SIGNAL \inst|add_rtl_5|adder|result_node|cs_buffer[1]\ : std_logic;
SIGNAL \inst|add_rtl_4|adder|result_node|cout[0]\ : std_logic;
SIGNAL \inst|add_rtl_4|adder|result_node|cs_buffer[1]\ : std_logic;
SIGNAL \inst|PASTEP[7]\ : std_logic;
SIGNAL \inst|add_rtl_5|adder|result_node|cout[1]\ : std_logic;
SIGNAL \inst|add_rtl_5|adder|result_node|cs_buffer[2]\ : std_logic;
SIGNAL \inst|add_rtl_4|adder|result_node|cout[1]\ : std_logic;
SIGNAL \inst|add_rtl_4|adder|result_node|cs_buffer[2]\ : std_logic;
SIGNAL \inst|PASTEP[8]\ : std_logic;
SIGNAL \inst|add_rtl_5|adder|result_node|cout[2]\ : std_logic;
SIGNAL \inst|add_rtl_5|adder|result_node|cs_buffer[3]\ : std_logic;
SIGNAL \inst|add_rtl_4|adder|result_node|cout[2]\ : std_logic;
SIGNAL \inst|add_rtl_4|adder|result_node|cs_buffer[3]\ : std_logic;
SIGNAL \inst|PASTEP[9]\ : std_logic;
SIGNAL \inst|add_rtl_5|adder|result_node|cout[3]\ : std_logic;
SIGNAL \inst|add_rtl_5|adder|result_node|cs_buffer[4]\ : std_logic;
SIGNAL \inst|add_rtl_4|adder|result_node|cout[3]\ : std_logic;
SIGNAL \inst|add_rtl_4|adder|result_node|cs_buffer[4]\ : std_logic;
SIGNAL \inst|PASTEP[10]\ : std_logic;
SIGNAL \inst|add_rtl_5|adder|result_node|cout[4]\ : std_logic;
SIGNAL \inst|add_rtl_5|adder|result_node|cs_buffer[5]\ : std_logic;
SIGNAL \inst|add_rtl_4|adder|result_node|cout[4]\ : std_logic;
SIGNAL \inst|add_rtl_4|adder|result_node|cs_buffer[5]\ : std_logic;
SIGNAL \inst|PASTEP[11]\ : std_logic;
SIGNAL \inst|add_rtl_5|adder|result_node|cout[5]\ : std_logic;
SIGNAL \inst|add_rtl_5|adder|result_node|cs_buffer[6]\ : std_logic;
SIGNAL \inst|add_rtl_4|adder|result_node|cout[5]\ : std_logic;
SIGNAL \inst|add_rtl_4|adder|result_node|cs_buffer[6]\ : std_logic;
SIGNAL \inst|PASTEP[12]\ : std_logic;
SIGNAL \inst|add_rtl_5|adder|result_node|cout[6]\ : std_logic;
SIGNAL \inst|add_rtl_5|adder|result_node|cs_buffer[7]\ : std_logic;
SIGNAL \inst|add_rtl_4|adder|result_node|cout[6]\ : std_logic;
SIGNAL \inst|add_rtl_4|adder|result_node|cs_buffer[7]\ : std_logic;
SIGNAL \inst|PASTEP[13]\ : std_logic;
SIGNAL \inst|add_rtl_5|adder|result_node|cout[7]\ : std_logic;
SIGNAL \inst|add_rtl_5|adder|result_node|cs_buffer[8]\ : std_logic;
SIGNAL \inst|add_rtl_4|adder|result_node|cout[7]\ : std_logic;
SIGNAL \inst|add_rtl_4|adder|result_node|cs_buffer[8]\ : std_logic;
SIGNAL \inst|PASTEP[14]\ : std_logic;
SIGNAL \inst|add_rtl_5|adder|result_node|cout[8]\ : std_logic;
SIGNAL \inst|add_rtl_5|adder|result_node|cs_buffer[9]\ : std_logic;
SIGNAL \inst|add_rtl_4|adder|result_node|cout[8]\ : std_logic;
SIGNAL \inst|add_rtl_4|adder|result_node|cs_buffer[9]\ : std_logic;
SIGNAL \inst|PASTEP[15]\ : std_logic;
SIGNAL \inst|add_rtl_5|adder|result_node|cout[9]\ : std_logic;
SIGNAL \inst|add_rtl_5|adder|result_node|cs_buffer[10]\ : std_logic;
SIGNAL \inst|add_rtl_4|adder|result_node|cout[9]\ : std_logic;
SIGNAL \inst|add_rtl_4|adder|result_node|cs_buffer[10]\ : std_logic;
SIGNAL \inst|PASTEP[16]\ : std_logic;
SIGNAL \inst|add_rtl_5|adder|result_node|cout[10]\ : std_logic;
SIGNAL \inst|add_rtl_5|adder|result_node|cs_buffer[11]\ : std_logic;
SIGNAL \inst|add_rtl_4|adder|result_node|cout[10]\ : std_logic;
SIGNAL \inst|add_rtl_4|adder|result_node|cs_buffer[11]\ : std_logic;
SIGNAL \inst|PASTEP[17]\ : std_logic;
SIGNAL \inst|add_rtl_5|adder|result_node|cout[11]\ : std_logic;
SIGNAL \inst|add_rtl_5|adder|result_node|cs_buffer[12]\ : std_logic;
SIGNAL \inst|add_rtl_4|adder|result_node|cout[11]\ : std_logic;
SIGNAL \inst|add_rtl_4|adder|result_node|cs_buffer[12]\ : std_logic;
SIGNAL \inst|PASTEP[18]\ : std_logic;
SIGNAL \inst|add_rtl_3|adder|result_node|cs_buffer[0]\ : std_logic;
SIGNAL \inst|PAREG[6]\ : std_logic;
SIGNAL \inst|add_rtl_3|adder|result_node|cout[0]\ : std_logic;
SIGNAL \inst|add_rtl_3|adder|result_node|cout[1]\ : std_logic;
SIGNAL \inst|add_rtl_3|adder|result_node|cout[2]\ : std_logic;
SIGNAL \inst|add_rtl_3|adder|result_node|cout[3]\ : std_logic;
SIGNAL \inst|add_rtl_3|adder|result_node|cout[4]\ : std_logic;
SIGNAL \inst|add_rtl_3|adder|result_node|cout[5]\ : std_logic;
SIGNAL \inst|add_rtl_3|adder|result_node|cout[6]\ : std_logic;
SIGNAL \inst|add_rtl_3|adder|result_node|cout[7]\ : std_logic;
SIGNAL \inst|add_rtl_3|adder|result_node|cout[8]\ : std_logic;
SIGNAL \inst|add_rtl_3|adder|result_node|cout[9]\ : std_logic;
SIGNAL \inst|add_rtl_3|adder|result_node|cout[10]\ : std_logic;
SIGNAL \inst|add_rtl_3|adder|result_node|cout[11]\ : std_logic;
SIGNAL \inst|add_rtl_3|adder|result_node|cs_buffer[12]\ : std_logic;
SIGNAL \inst|PAREG[18]\ : std_logic;
SIGNAL \inst|add_rtl_5|adder|result_node|cout[12]\ : std_logic;
SIGNAL \inst|add_rtl_5|adder|result_node|cs_buffer[13]\ : std_logic;
SIGNAL \inst|add_rtl_4|adder|result_node|cout[12]\ : std_logic;
SIGNAL \inst|add_rtl_4|adder|result_node|cs_buffer[13]\ : std_logic;
SIGNAL \inst|PASTEP[19]\ : std_logic;
SIGNAL \inst|add_rtl_3|adder|result_node|cout[12]\ : std_logic;
SIGNAL \inst|add_rtl_3|adder|result_node|cs_buffer[13]\ : std_logic;
SIGNAL \inst|PAREG[19]\ : std_logic;
SIGNAL \inst|add_rtl_5|adder|result_node|cout[13]\ : std_logic;
SIGNAL \inst|add_rtl_5|adder|result_node|cs_buffer[14]\ : std_logic;
SIGNAL \inst|add_rtl_4|adder|result_node|cout[13]\ : std_logic;
SIGNAL \inst|add_rtl_4|adder|result_node|cs_buffer[14]\ : std_logic;
SIGNAL \inst|PASTEP[20]\ : std_logic;
SIGNAL \inst|add_rtl_3|adder|result_node|cout[13]\ : std_logic;
SIGNAL \inst|add_rtl_3|adder|result_node|cs_buffer[14]\ : std_logic;
SIGNAL \inst|PAREG[20]\ : std_logic;
SIGNAL \inst|add_rtl_5|adder|result_node|cout[14]\ : std_logic;
SIGNAL \inst|add_rtl_5|adder|result_node|cs_buffer[15]\ : std_logic;
SIGNAL \inst|add_rtl_4|adder|result_node|cout[14]\ : std_logic;
SIGNAL \inst|add_rtl_4|adder|result_node|cs_buffer[15]\ : std_logic;
SIGNAL \inst|PASTEP[21]\ : std_logic;
SIGNAL \inst|add_rtl_3|adder|result_node|cout[14]\ : std_logic;
SIGNAL \inst|add_rtl_3|adder|result_node|cs_buffer[15]\ : std_logic;
SIGNAL \inst|PAREG[21]\ : std_logic;
SIGNAL \inst|add_rtl_5|adder|result_node|cout[15]\ : std_logic;
SIGNAL \inst|add_rtl_5|adder|result_node|cs_buffer[16]\ : std_logic;
SIGNAL \inst|add_rtl_4|adder|result_node|cout[15]\ : std_logic;
SIGNAL \inst|add_rtl_4|adder|result_node|cs_buffer[16]\ : std_logic;
SIGNAL \inst|PASTEP[22]\ : std_logic;
SIGNAL \inst|add_rtl_3|adder|result_node|cout[15]\ : std_logic;
SIGNAL \inst|add_rtl_3|adder|result_node|cs_buffer[16]\ : std_logic;
SIGNAL \inst|PAREG[22]\ : std_logic;
SIGNAL \inst|add_rtl_5|adder|result_node|cout[16]\ : std_logic;
SIGNAL \inst|add_rtl_5|adder|unreg_res_node[17]\ : std_logic;
SIGNAL \inst|add_rtl_4|adder|result_node|cout[16]\ : std_logic;
SIGNAL \inst|add_rtl_4|adder|unreg_res_node[17]\ : std_logic;
SIGNAL \inst|PASTEP[23]\ : std_logic;
SIGNAL \inst|add_rtl_3|adder|result_node|cout[16]\ : std_logic;
SIGNAL \inst|add_rtl_3|adder|unreg_res_node[17]\ : std_logic;
SIGNAL \inst|PAREG[23]\ : std_logic;
SIGNAL \inst3|lpm_rom_component|srom|q[0]\ : std_logic;
SIGNAL \PathSel[2]~dataout\ : std_logic;
SIGNAL \inst5|sanjiaoreg[0]\ : std_logic;
SIGNAL \inst1|lpm_rom_component|srom|q[0]\ : std_logic;
SIGNAL \PathSel[0]~dataout\ : std_logic;
SIGNAL \inst5|sinreg[0]\ : std_logic;
SIGNAL \inst2|lpm_rom_component|srom|q[0]\ : std_logic;
SIGNAL \PathSel[1]~dataout\ : std_logic;
SIGNAL \inst5|juchireg[0]\ : std_logic;
SIGNAL \inst5|add_rtl_0|adder|result_node|cs_buffer[0]~142\ : std_logic;
SIGNAL \inst5|add_rtl_1|adder|result_node|cs_buffer[0]~173\ : std_logic;