rtlc.args

设计与验证Verilog_实例

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RTLCompiler invoked with options:
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-main work.single_if  -thr_opt -out_dir C:/prj/Example-4-10/if_single/PrecisionRTL/if_single_temp_1//rtlc.out  -no_drc -hdl verilog  -fsm_opt -2000 -xprobe -infer_rom -xor_eq_opt -flatten_or 0  -infer_mem precision  -one_hot_enc -tech_map -infer_counter 2  -pri_enc_opt -no_add3_opt -pconst_prop -allow_WFU -allow_FSW -allow_UFO -flatten_and 0  -force_all -allow_4ST -mux_factor_opt -no_addbuf_opt -pipe_flow -allow_GSD -fast_partition -msgpipefdr 196  -res_share -vecwriteopt -driver_pid 2408@cceieigjbg  -allow_CVD -allow_FRN -ctrl_mux_flat never  -xdbpipefdr 160  -allow_MDR -use_sync_dff -msgpipefdw 324  -new_mux_flow -allow_ISL -if_els_if_mod -disable_opt -infer_case_op 2  -new_mux_costing -xdbpipefdw 168  -aggressive_rom -fpga_technology lattice_ec  -no_cross_share -fsm_opt_thru_hier -disable_incr -implicit_state opt  -encoding_style auto  -use_enable_dff -ctrl_sub_prog_flat 1024  -preserve_mults -exemplar_best -new_or_simplify -upper_enum_break 800  -infer_var_shifters -lower_enum_break 5  -xilinx_tech_map -generic_shine_thru -disable_dumps -barrel_shifter_opt -res_share_mux_opt -bundle_instances -inline_flatten_proc -exemplar_eval 1  -bind_mem_instances -mux_anded_sel_opt -gnd_hanging_terminals -enable_time_support -dont_infer_sel_counters -precision_port_style -mux_factor_sel_cone_opt -if_else_if_for_condasgn -aggressive_if2case -acceptance_level medium  -preserve_name_case -enable_size_check -enable_case_pragmas -relaxed_mem_checks -hdl_array_name_style %s(%d)  -enable_BHV_messages -simple_vecwrite_impl -legalize_module_names -set_evaluated_return_size -retain_bbox_param_value_type -partial_sanity_for_techcells -evaluate_decls_in_generates 
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