texitype_select.tan.qmsg

来自「基于fpga的出租车计费系统」· QMSG 代码 · 共 9 行 · 第 1/2 页

{ "Info" "ITDB_FULL_TCO_RESULT" "clk oclk temp\[3\] 8.124 ns register " "Info: tco from clock \"clk\" to destination pin \"oclk\" through register \"temp\[3\]\" is 8.124 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.698 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.698 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "texitype_select.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/texitype_select/texitype_select.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G3 6 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 6; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "texitype_select.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/texitype_select/texitype_select.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.044 ns) + CELL(0.537 ns) 2.698 ns temp\[3\] 3 REG LCFF_X31_Y35_N7 4 " "Info: 3: + IC(1.044 ns) + CELL(0.537 ns) = 2.698 ns; Loc. = LCFF_X31_Y35_N7; Fanout = 4; REG Node = 'temp\[3\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.581 ns" { clk~clkctrl temp[3] } "NODE_NAME" } } { "texitype_select.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/texitype_select/texitype_select.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 56.93 % ) " "Info: Total cell delay = 1.536 ns ( 56.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.162 ns ( 43.07 % ) " "Info: Total interconnect delay = 1.162 ns ( 43.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.698 ns" { clk clk~clkctrl temp[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.698 ns" { clk clk~combout clk~clkctrl temp[3] } { 0.000ns 0.000ns 0.118ns 1.044ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "texitype_select.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/texitype_select/texitype_select.vhd" 26 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.176 ns + Longest register pin " "Info: + Longest register to pin delay is 5.176 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns temp\[3\] 1 REG LCFF_X31_Y35_N7 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X31_Y35_N7; Fanout = 4; REG Node = 'temp\[3\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { temp[3] } "NODE_NAME" } } { "texitype_select.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/texitype_select/texitype_select.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.738 ns) + CELL(0.438 ns) 1.176 ns Equal4~387 2 COMB LCCOMB_X31_Y35_N26 1 " "Info: 2: + IC(0.738 ns) + CELL(0.438 ns) = 1.176 ns; Loc. = LCCOMB_X31_Y35_N26; Fanout = 1; COMB Node = 'Equal4~387'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.176 ns" { temp[3] Equal4~387 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.250 ns) + CELL(0.393 ns) 1.819 ns Equal4~390 3 COMB LCCOMB_X31_Y35_N0 1 " "Info: 3: + IC(0.250 ns) + CELL(0.393 ns) = 1.819 ns; Loc. = LCCOMB_X31_Y35_N0; Fanout = 1; COMB Node = 'Equal4~390'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.643 ns" { Equal4~387 Equal4~390 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.569 ns) + CELL(2.788 ns) 5.176 ns oclk 4 PIN PIN_B12 0 " "Info: 4: + IC(0.569 ns) + CELL(2.788 ns) = 5.176 ns; Loc. = PIN_B12; Fanout = 0; PIN Node = 'oclk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.357 ns" { Equal4~390 oclk } "NODE_NAME" } } { "texitype_select.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/texitype_select/texitype_select.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.619 ns ( 69.92 % ) " "Info: Total cell delay = 3.619 ns ( 69.92 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.557 ns ( 30.08 % ) " "Info: Total interconnect delay = 1.557 ns ( 30.08 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.176 ns" { temp[3] Equal4~387 Equal4~390 oclk } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.176 ns" { temp[3] Equal4~387 Equal4~390 oclk } { 0.000ns 0.738ns 0.250ns 0.569ns } { 0.000ns 0.438ns 0.393ns 2.788ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.698 ns" { clk clk~clkctrl temp[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.698 ns" { clk clk~combout clk~clkctrl temp[3] } { 0.000ns 0.000ns 0.118ns 1.044ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.176 ns" { temp[3] Equal4~387 Equal4~390 oclk } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.176 ns" { temp[3] Equal4~387 Equal4~390 oclk } { 0.000ns 0.738ns 0.250ns 0.569ns } { 0.000ns 0.438ns 0.393ns 2.788ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "cartype\[1\] oclk 5.912 ns Longest " "Info: Longest tpd from source pin \"cartype\[1\]\" to destination pin \"oclk\" is 5.912 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns cartype\[1\] 1 PIN PIN_D13 4 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_D13; Fanout = 4; PIN Node = 'cartype\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { cartype[1] } "NODE_NAME" } } { "texitype_select.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/texitype_select/texitype_select.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.658 ns) + CELL(0.275 ns) 1.912 ns Equal4~387 2 COMB LCCOMB_X31_Y35_N26 1 " "Info: 2: + IC(0.658 ns) + CELL(0.275 ns) = 1.912 ns; Loc. = LCCOMB_X31_Y35_N26; Fanout = 1; COMB Node = 'Equal4~387'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.933 ns" { cartype[1] Equal4~387 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.250 ns) + CELL(0.393 ns) 2.555 ns Equal4~390 3 COMB LCCOMB_X31_Y35_N0 1 " "Info: 3: + IC(0.250 ns) + CELL(0.393 ns) = 2.555 ns; Loc. = LCCOMB_X31_Y35_N0; Fanout = 1; COMB Node = 'Equal4~390'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.643 ns" { Equal4~387 Equal4~390 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.569 ns) + CELL(2.788 ns) 5.912 ns oclk 4 PIN PIN_B12 0 " "Info: 4: + IC(0.569 ns) + CELL(2.788 ns) = 5.912 ns; Loc. = PIN_B12; Fanout = 0; PIN Node = 'oclk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.357 ns" { Equal4~390 oclk } "NODE_NAME" } } { "texitype_select.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/texitype_select/texitype_select.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.435 ns ( 75.02 % ) " "Info: Total cell delay = 4.435 ns ( 75.02 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.477 ns ( 24.98 % ) " "Info: Total interconnect delay = 1.477 ns ( 24.98 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.912 ns" { cartype[1] Equal4~387 Equal4~390 oclk } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.912 ns" { cartype[1] cartype[1]~combout Equal4~387 Equal4~390 oclk } { 0.000ns 0.000ns 0.658ns 0.250ns 0.569ns } { 0.000ns 0.979ns 0.275ns 0.393ns 2.788ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Oct 08 11:07:02 2008 " "Info: Processing ended: Wed Oct 08 11:07:02 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}