texitype_select.tan.rpt

来自「基于fpga的出租车计费系统」· RPT 代码 · 共 203 行 · 第 1/2 页

; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; temp[4] ; temp[5] ; clk        ; clk      ; None                        ; None                      ; 1.201 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; temp[2] ; temp[3] ; clk        ; clk      ; None                        ; None                      ; 1.200 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; temp[0] ; temp[1] ; clk        ; clk      ; None                        ; None                      ; 0.861 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; temp[3] ; temp[3] ; clk        ; clk      ; None                        ; None                      ; 0.858 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; temp[1] ; temp[1] ; clk        ; clk      ; None                        ; None                      ; 0.821 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; temp[4] ; temp[4] ; clk        ; clk      ; None                        ; None                      ; 0.818 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; temp[2] ; temp[2] ; clk        ; clk      ; None                        ; None                      ; 0.817 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; temp[5] ; temp[5] ; clk        ; clk      ; None                        ; None                      ; 0.549 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; temp[0] ; temp[0] ; clk        ; clk      ; None                        ; None                      ; 0.407 ns                ;
+-------+------------------------------------------------+---------+---------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-----------------------------------------------------------------+
; tco                                                             ;
+-------+--------------+------------+---------+------+------------+
; Slack ; Required tco ; Actual tco ; From    ; To   ; From Clock ;
+-------+--------------+------------+---------+------+------------+
; N/A   ; None         ; 8.124 ns   ; temp[3] ; oclk ; clk        ;
; N/A   ; None         ; 7.887 ns   ; temp[2] ; oclk ; clk        ;
; N/A   ; None         ; 7.599 ns   ; temp[1] ; oclk ; clk        ;
; N/A   ; None         ; 7.447 ns   ; temp[0] ; oclk ; clk        ;
; N/A   ; None         ; 7.318 ns   ; temp[4] ; oclk ; clk        ;
; N/A   ; None         ; 7.051 ns   ; temp[5] ; oclk ; clk        ;
+-------+--------------+------------+---------+------+------------+


+-----------------------------------------------------------------+
; tpd                                                             ;
+-------+-------------------+-----------------+------------+------+
; Slack ; Required P2P Time ; Actual P2P Time ; From       ; To   ;
+-------+-------------------+-----------------+------------+------+
; N/A   ; None              ; 5.912 ns        ; cartype[1] ; oclk ;
; N/A   ; None              ; 5.785 ns        ; cartype[0] ; oclk ;
+-------+-------------------+-----------------+------------+------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Wed Oct 08 11:07:02 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off texitype_select -c texitype_select --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 420.17 MHz between source register "temp[0]" and destination register "temp[5]"
    Info: fmax restricted to clock pin edge rate 2.38 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.461 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X31_Y35_N21; Fanout = 5; REG Node = 'temp[0]'
            Info: 2: + IC(0.340 ns) + CELL(0.414 ns) = 0.754 ns; Loc. = LCCOMB_X31_Y35_N2; Fanout = 2; COMB Node = 'temp[1]~27'
            Info: 3: + IC(0.000 ns) + CELL(0.071 ns) = 0.825 ns; Loc. = LCCOMB_X31_Y35_N4; Fanout = 2; COMB Node = 'temp[2]~28'
            Info: 4: + IC(0.000 ns) + CELL(0.071 ns) = 0.896 ns; Loc. = LCCOMB_X31_Y35_N6; Fanout = 2; COMB Node = 'temp[3]~29'
            Info: 5: + IC(0.000 ns) + CELL(0.071 ns) = 0.967 ns; Loc. = LCCOMB_X31_Y35_N8; Fanout = 1; COMB Node = 'temp[4]~30'
            Info: 6: + IC(0.000 ns) + CELL(0.410 ns) = 1.377 ns; Loc. = LCCOMB_X31_Y35_N10; Fanout = 1; COMB Node = 'temp[5]~23'
            Info: 7: + IC(0.000 ns) + CELL(0.084 ns) = 1.461 ns; Loc. = LCFF_X31_Y35_N11; Fanout = 3; REG Node = 'temp[5]'
            Info: Total cell delay = 1.121 ns ( 76.73 % )
            Info: Total interconnect delay = 0.340 ns ( 23.27 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.698 ns
                Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 6; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(1.044 ns) + CELL(0.537 ns) = 2.698 ns; Loc. = LCFF_X31_Y35_N11; Fanout = 3; REG Node = 'temp[5]'
                Info: Total cell delay = 1.536 ns ( 56.93 % )
                Info: Total interconnect delay = 1.162 ns ( 43.07 % )
            Info: - Longest clock path from clock "clk" to source register is 2.698 ns
                Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 6; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(1.044 ns) + CELL(0.537 ns) = 2.698 ns; Loc. = LCFF_X31_Y35_N21; Fanout = 5; REG Node = 'temp[0]'
                Info: Total cell delay = 1.536 ns ( 56.93 % )
                Info: Total interconnect delay = 1.162 ns ( 43.07 % )
        Info: + Micro clock to output delay of source is 0.250 ns
        Info: + Micro setup delay of destination is -0.036 ns
Info: tco from clock "clk" to destination pin "oclk" through register "temp[3]" is 8.124 ns
    Info: + Longest clock path from clock "clk" to source register is 2.698 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 6; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(1.044 ns) + CELL(0.537 ns) = 2.698 ns; Loc. = LCFF_X31_Y35_N7; Fanout = 4; REG Node = 'temp[3]'
        Info: Total cell delay = 1.536 ns ( 56.93 % )
        Info: Total interconnect delay = 1.162 ns ( 43.07 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Longest register to pin delay is 5.176 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X31_Y35_N7; Fanout = 4; REG Node = 'temp[3]'
        Info: 2: + IC(0.738 ns) + CELL(0.438 ns) = 1.176 ns; Loc. = LCCOMB_X31_Y35_N26; Fanout = 1; COMB Node = 'Equal4~387'
        Info: 3: + IC(0.250 ns) + CELL(0.393 ns) = 1.819 ns; Loc. = LCCOMB_X31_Y35_N0; Fanout = 1; COMB Node = 'Equal4~390'
        Info: 4: + IC(0.569 ns) + CELL(2.788 ns) = 5.176 ns; Loc. = PIN_B12; Fanout = 0; PIN Node = 'oclk'
        Info: Total cell delay = 3.619 ns ( 69.92 % )
        Info: Total interconnect delay = 1.557 ns ( 30.08 % )
Info: Longest tpd from source pin "cartype[1]" to destination pin "oclk" is 5.912 ns
    Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_D13; Fanout = 4; PIN Node = 'cartype[1]'
    Info: 2: + IC(0.658 ns) + CELL(0.275 ns) = 1.912 ns; Loc. = LCCOMB_X31_Y35_N26; Fanout = 1; COMB Node = 'Equal4~387'
    Info: 3: + IC(0.250 ns) + CELL(0.393 ns) = 2.555 ns; Loc. = LCCOMB_X31_Y35_N0; Fanout = 1; COMB Node = 'Equal4~390'
    Info: 4: + IC(0.569 ns) + CELL(2.788 ns) = 5.912 ns; Loc. = PIN_B12; Fanout = 0; PIN Node = 'oclk'
    Info: Total cell delay = 4.435 ns ( 75.02 % )
    Info: Total interconnect delay = 1.477 ns ( 24.98 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Wed Oct 08 11:07:02 2008
    Info: Elapsed time: 00:00:01