count_distance.tan.qmsg

基于fpga的出租车计费系统

{ "Info" "ITDB_FULL_TCO_RESULT" "clkin length\[5\] temp0\[0\] 11.416 ns register " "Info: tco from clock \"clkin\" to destination pin \"length\[5\]\" through register \"temp0\[0\]\" is 11.416 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin source 2.666 ns + Longest register " "Info: + Longest clock path from clock \"clkin\" to source register is 2.666 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clkin 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clkin'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clkin } "NODE_NAME" } } { "count_distance.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/count_distance/count_distance.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clkin~clkctrl 2 COMB CLKCTRL_G3 20 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 20; COMB Node = 'clkin~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clkin clkin~clkctrl } "NODE_NAME" } } { "count_distance.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/count_distance/count_distance.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.012 ns) + CELL(0.537 ns) 2.666 ns temp0\[0\] 3 REG LCFF_X28_Y11_N1 5 " "Info: 3: + IC(1.012 ns) + CELL(0.537 ns) = 2.666 ns; Loc. = LCFF_X28_Y11_N1; Fanout = 5; REG Node = 'temp0\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.549 ns" { clkin~clkctrl temp0[0] } "NODE_NAME" } } { "count_distance.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/count_distance/count_distance.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.61 % ) " "Info: Total cell delay = 1.536 ns ( 57.61 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.130 ns ( 42.39 % ) " "Info: Total interconnect delay = 1.130 ns ( 42.39 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.666 ns" { clkin clkin~clkctrl temp0[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.666 ns" { clkin clkin~combout clkin~clkctrl temp0[0] } { 0.000ns 0.000ns 0.118ns 1.012ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "count_distance.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/count_distance/count_distance.vhd" 27 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.500 ns + Longest register pin " "Info: + Longest register to pin delay is 8.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns temp0\[0\] 1 REG LCFF_X28_Y11_N1 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X28_Y11_N1; Fanout = 5; REG Node = 'temp0\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { temp0[0] } "NODE_NAME" } } { "count_distance.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/count_distance/count_distance.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.015 ns) + CELL(0.393 ns) 1.408 ns LessThan1~126 2 COMB LCCOMB_X27_Y12_N0 1 " "Info: 2: + IC(1.015 ns) + CELL(0.393 ns) = 1.408 ns; Loc. = LCCOMB_X27_Y12_N0; Fanout = 1; COMB Node = 'LessThan1~126'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.408 ns" { temp0[0] LessThan1~126 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1547 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.479 ns LessThan1~128 3 COMB LCCOMB_X27_Y12_N2 1 " "Info: 3: + IC(0.000 ns) + CELL(0.071 ns) = 1.479 ns; Loc. = LCCOMB_X27_Y12_N2; Fanout = 1; COMB Node = 'LessThan1~128'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { LessThan1~126 LessThan1~128 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1547 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.550 ns LessThan1~130 4 COMB LCCOMB_X27_Y12_N4 1 " "Info: 4: + IC(0.000 ns) + CELL(0.071 ns) = 1.550 ns; Loc. = LCCOMB_X27_Y12_N4; Fanout = 1; COMB Node = 'LessThan1~130'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { LessThan1~128 LessThan1~130 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1547 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.621 ns LessThan1~132 5 COMB LCCOMB_X27_Y12_N6 1 " "Info: 5: + IC(0.000 ns) + CELL(0.071 ns) = 1.621 ns; Loc. = LCCOMB_X27_Y12_N6; Fanout = 1; COMB Node = 'LessThan1~132'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { LessThan1~130 LessThan1~132 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1547 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.692 ns LessThan1~134 6 COMB LCCOMB_X27_Y12_N8 1 " "Info: 6: + IC(0.000 ns) + CELL(0.071 ns) = 1.692 ns; Loc. = LCCOMB_X27_Y12_N8; Fanout = 1; COMB Node = 'LessThan1~134'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { LessThan1~132 LessThan1~134 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1547 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.763 ns LessThan1~136 7 COMB LCCOMB_X27_Y12_N10 1 " "Info: 7: + IC(0.000 ns) + CELL(0.071 ns) = 1.763 ns; Loc. = LCCOMB_X27_Y12_N10; Fanout = 1; COMB Node = 'LessThan1~136'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { LessThan1~134 LessThan1~136 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1547 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 2.173 ns LessThan1~137 8 COMB LCCOMB_X27_Y12_N12 7 " "Info: 8: + IC(0.000 ns) + CELL(0.410 ns) = 2.173 ns; Loc. = LCCOMB_X27_Y12_N12; Fanout = 7; COMB Node = 'LessThan1~137'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.410 ns" { LessThan1~136 LessThan1~137 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1547 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.740 ns) + CELL(0.437 ns) 3.350 ns length~475 9 COMB LCCOMB_X29_Y12_N2 1 " "Info: 9: + IC(0.740 ns) + CELL(0.437 ns) = 3.350 ns; Loc. = LCCOMB_X29_Y12_N2; Fanout = 1; COMB Node = 'length~475'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.177 ns" { LessThan1~137 length~475 } "NODE_NAME" } } { "count_distance.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/count_distance/count_distance.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.528 ns) + CELL(2.622 ns) 8.500 ns length\[5\] 10 PIN PIN_R19 0 " "Info: 10: + IC(2.528 ns) + CELL(2.622 ns) = 8.500 ns; Loc. = PIN_R19; Fanout = 0; PIN Node = 'length\[5\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.150 ns" { length~475 length[5] } "NODE_NAME" } } { "count_distance.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/count_distance/count_distance.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.217 ns ( 49.61 % ) " "Info: Total cell delay = 4.217 ns ( 49.61 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.283 ns ( 50.39 % ) " "Info: Total interconnect delay = 4.283 ns ( 50.39 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.500 ns" { temp0[0] LessThan1~126 LessThan1~128 LessThan1~130 LessThan1~132 LessThan1~134 LessThan1~136 LessThan1~137 length~475 length[5] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "8.500 ns" { temp0[0] LessThan1~126 LessThan1~128 LessThan1~130 LessThan1~132 LessThan1~134 LessThan1~136 LessThan1~137 length~475 length[5] } { 0.000ns 1.015ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.740ns 2.528ns } { 0.000ns 0.393ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.410ns 0.437ns 2.622ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.666 ns" { clkin clkin~clkctrl temp0[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.666 ns" { clkin clkin~combout clkin~clkctrl temp0[0] } { 0.000ns 0.000ns 0.118ns 1.012ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.500 ns" { temp0[0] LessThan1~126 LessThan1~128 LessThan1~130 LessThan1~132 LessThan1~134 LessThan1~136 LessThan1~137 length~475 length[5] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "8.500 ns" { temp0[0] LessThan1~126 LessThan1~128 LessThan1~130 LessThan1~132 LessThan1~134 LessThan1~136 LessThan1~137 length~475 length[5] } { 0.000ns 1.015ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.740ns 2.528ns } { 0.000ns 0.393ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.410ns 0.437ns 2.622ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "dip\[0\] length\[5\] 14.937 ns Longest " "Info: Longest tpd from source pin \"dip\[0\]\" to destination pin \"length\[5\]\" is 14.937 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.842 ns) 0.842 ns dip\[0\] 1 PIN PIN_U9 7 " "Info: 1: + IC(0.000 ns) + CELL(0.842 ns) = 0.842 ns; Loc. = PIN_U9; Fanout = 7; PIN Node = 'dip\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { dip[0] } "NODE_NAME" } } { "count_distance.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/count_distance/count_distance.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.625 ns) + CELL(0.438 ns) 6.905 ns Mux4~12 2 COMB LCCOMB_X29_Y12_N8 3 " "Info: 2: + IC(5.625 ns) + CELL(0.438 ns) = 6.905 ns; Loc. = LCCOMB_X29_Y12_N8; Fanout = 3; COMB Node = 'Mux4~12'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.063 ns" { dip[0] Mux4~12 } "NODE_NAME" } } { "count_distance.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/count_distance/count_distance.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.689 ns) + CELL(0.393 ns) 7.987 ns LessThan1~130 3 COMB LCCOMB_X27_Y12_N4 1 " "Info: 3: + IC(0.689 ns) + CELL(0.393 ns) = 7.987 ns; Loc. = LCCOMB_X27_Y12_N4; Fanout = 1; COMB Node = 'LessThan1~130'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.082 ns" { Mux4~12 LessThan1~130 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1547 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 8.058 ns LessThan1~132 4 COMB LCCOMB_X27_Y12_N6 1 " "Info: 4: + IC(0.000 ns) + CELL(0.071 ns) = 8.058 ns; Loc. = LCCOMB_X27_Y12_N6; Fanout = 1; COMB Node = 'LessThan1~132'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { LessThan1~130 LessThan1~132 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1547 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 8.129 ns LessThan1~134 5 COMB LCCOMB_X27_Y12_N8 1 " "Info: 5: + IC(0.000 ns) + CELL(0.071 ns) = 8.129 ns; Loc. = LCCOMB_X27_Y12_N8; Fanout = 1; COMB Node = 'LessThan1~134'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { LessThan1~132 LessThan1~134 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1547 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 8.200 ns LessThan1~136 6 COMB LCCOMB_X27_Y12_N10 1 " "Info: 6: + IC(0.000 ns) + CELL(0.071 ns) = 8.200 ns; Loc. = LCCOMB_X27_Y12_N10; Fanout = 1; COMB Node = 'LessThan1~136'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { LessThan1~134 LessThan1~136 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1547 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 8.610 ns LessThan1~137 7 COMB LCCOMB_X27_Y12_N12 7 " "Info: 7: + IC(0.000 ns) + CELL(0.410 ns) = 8.610 ns; Loc. = LCCOMB_X27_Y12_N12; Fanout = 7; COMB Node = 'LessThan1~137'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.410 ns" { LessThan1~136 LessThan1~137 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1547 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.740 ns) + CELL(0.437 ns) 9.787 ns length~475 8 COMB LCCOMB_X29_Y12_N2 1 " "Info: 8: + IC(0.740 ns) + CELL(0.437 ns) = 9.787 ns; Loc. = LCCOMB_X29_Y12_N2; Fanout = 1; COMB Node = 'length~475'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.177 ns" { LessThan1~137 length~475 } "NODE_NAME" } } { "count_distance.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/count_distance/count_distance.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.528 ns) + CELL(2.622 ns) 14.937 ns length\[5\] 9 PIN PIN_R19 0 " "Info: 9: + IC(2.528 ns) + CELL(2.622 ns) = 14.937 ns; Loc. = PIN_R19; Fanout = 0; PIN Node = 'length\[5\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.150 ns" { length~475 length[5] } "NODE_NAME" } } { "count_distance.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/count_distance/count_distance.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.355 ns ( 35.85 % ) " "Info: Total cell delay = 5.355 ns ( 35.85 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.582 ns ( 64.15 % ) " "Info: Total interconnect delay = 9.582 ns ( 64.15 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "14.937 ns" { dip[0] Mux4~12 LessThan1~130 LessThan1~132 LessThan1~134 LessThan1~136 LessThan1~137 length~475 length[5] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "14.937 ns" { dip[0] dip[0]~combout Mux4~12 LessThan1~130 LessThan1~132 LessThan1~134 LessThan1~136 LessThan1~137 length~475 length[5] } { 0.000ns 0.000ns 5.625ns 0.689ns 0.000ns 0.000ns 0.000ns 0.000ns 0.740ns 2.528ns } { 0.000ns 0.842ns 0.438ns 0.393ns 0.071ns 0.071ns 0.071ns 0.410ns 0.437ns 2.622ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "temp1\[0\] dip\[1\] clkin -1.922 ns register " "Info: th for register \"temp1\[0\]\" (data pin = \"dip\[1\]\", clock pin = \"clkin\") is -1.922 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin destination 2.674 ns + Longest register " "Info: + Longest clock path from clock \"clkin\" to destination register is 2.674 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clkin 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clkin'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clkin } "NODE_NAME" } } { "count_distance.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/count_distance/count_distance.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clkin~clkctrl 2 COMB CLKCTRL_G3 20 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 20; COMB Node = 'clkin~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clkin clkin~clkctrl } "NODE_NAME" } } { "count_distance.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/count_distance/count_distance.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.020 ns) + CELL(0.537 ns) 2.674 ns temp1\[0\] 3 REG LCFF_X29_Y12_N5 5 " "Info: 3: + IC(1.020 ns) + CELL(0.537 ns) = 2.674 ns; Loc. = LCFF_X29_Y12_N5; Fanout = 5; REG Node = 'temp1\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.557 ns" { clkin~clkctrl temp1[0] } "NODE_NAME" } } { "count_distance.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/count_distance/count_distance.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.44 % ) " "Info: Total cell delay = 1.536 ns ( 57.44 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.138 ns ( 42.56 % ) " "Info: Total interconnect delay = 1.138 ns ( 42.56 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.674 ns" { clkin clkin~clkctrl temp1[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.674 ns" { clkin clkin~combout clkin~clkctrl temp1[0] } { 0.000ns 0.000ns 0.118ns 1.020ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "count_distance.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/count_distance/count_distance.vhd" 34 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.862 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.862 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns dip\[1\] 1 PIN PIN_C13 5 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_C13; Fanout = 5; PIN Node = 'dip\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { dip[1] } "NODE_NAME" } } { "count_distance.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/count_distance/count_distance.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.724 ns) + CELL(0.150 ns) 2.853 ns Mux2~108 2 COMB LCCOMB_X29_Y12_N22 3 " "Info: 2: + IC(1.724 ns) + CELL(0.150 ns) = 2.853 ns; Loc. = LCCOMB_X29_Y12_N22; Fanout = 3; COMB Node = 'Mux2~108'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.874 ns" { dip[1] Mux2~108 } "NODE_NAME" } } { "count_distance.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/count_distance/count_distance.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.455 ns) + CELL(0.393 ns) 3.701 ns LessThan0~139 3 COMB LCCOMB_X28_Y12_N6 1 " "Info: 3: + IC(0.455 ns) + CELL(0.393 ns) = 3.701 ns; Loc. = LCCOMB_X28_Y12_N6; Fanout = 1; COMB Node = 'LessThan0~139'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.848 ns" { Mux2~108 LessThan0~139 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1695 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 3.772 ns LessThan0~141 4 COMB LCCOMB_X28_Y12_N8 1 " "Info: 4: + IC(0.000 ns) + CELL(0.071 ns) = 3.772 ns; Loc. = LCCOMB_X28_Y12_N8; Fanout = 1; COMB Node = 'LessThan0~141'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { LessThan0~139 LessThan0~141 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1695 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 4.182 ns LessThan0~142 5 COMB LCCOMB_X28_Y12_N10 2 " "Info: 5: + IC(0.000 ns) + CELL(0.410 ns) = 4.182 ns; Loc. = LCCOMB_X28_Y12_N10; Fanout = 2; COMB Node = 'LessThan0~142'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.410 ns" { LessThan0~141 LessThan0~142 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1695 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.446 ns) + CELL(0.150 ns) 4.778 ns temp1\[0\]~355 6 COMB LCCOMB_X29_Y12_N4 1 " "Info: 6: + IC(0.446 ns) + CELL(0.150 ns) = 4.778 ns; Loc. = LCCOMB_X29_Y12_N4; Fanout = 1; COMB Node = 'temp1\[0\]~355'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.596 ns" { LessThan0~142 temp1[0]~355 } "NODE_NAME" } } { "count_distance.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/count_distance/count_distance.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 4.862 ns temp1\[0\] 7 REG LCFF_X29_Y12_N5 5 " "Info: 7: + IC(0.000 ns) + CELL(0.084 ns) = 4.862 ns; Loc. = LCFF_X29_Y12_N5; Fanout = 5; REG Node = 'temp1\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { temp1[0]~355 temp1[0] } "NODE_NAME" } } { "count_distance.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/count_distance/count_distance.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.237 ns ( 46.01 % ) " "Info: Total cell delay = 2.237 ns ( 46.01 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.625 ns ( 53.99 % ) " "Info: Total interconnect delay = 2.625 ns ( 53.99 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.862 ns" { dip[1] Mux2~108 LessThan0~139 LessThan0~141 LessThan0~142 temp1[0]~355 temp1[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.862 ns" { dip[1] dip[1]~combout Mux2~108 LessThan0~139 LessThan0~141 LessThan0~142 temp1[0]~355 temp1[0] } { 0.000ns 0.000ns 1.724ns 0.455ns 0.000ns 0.000ns 0.446ns 0.000ns } { 0.000ns 0.979ns 0.150ns 0.393ns 0.071ns 0.410ns 0.150ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.674 ns" { clkin clkin~clkctrl temp1[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.674 ns" { clkin clkin~combout clkin~clkctrl temp1[0] } { 0.000ns 0.000ns 0.118ns 1.020ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.862 ns" { dip[1] Mux2~108 LessThan0~139 LessThan0~141 LessThan0~142 temp1[0]~355 temp1[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.862 ns" { dip[1] dip[1]~combout Mux2~108 LessThan0~139 LessThan0~141 LessThan0~142 temp1[0]~355 temp1[0] } { 0.000ns 0.000ns 1.724ns 0.455ns 0.000ns 0.000ns 0.446ns 0.000ns } { 0.000ns 0.979ns 0.150ns 0.393ns 0.071ns 0.410ns 0.150ns 0.084ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}