📄 count_distance.tan.qmsg

📁 基于fpga的出租车计费系统
💻 QMSG
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{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clkin " "Info: Assuming node \"clkin\" is an undefined clock" {  } { { "count_distance.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/count_distance/count_distance.vhd" 7 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clkin" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clkin register temp0\[1\] register temp1\[2\] 323.31 MHz 3.093 ns Internal " "Info: Clock \"clkin\" has Internal fmax of 323.31 MHz between source register \"temp0\[1\]\" and destination register \"temp1\[2\]\" (period= 3.093 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.879 ns + Longest register register " "Info: + Longest register to register delay is 2.879 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns temp0\[1\] 1 REG LCFF_X27_Y12_N15 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X27_Y12_N15; Fanout = 5; REG Node = 'temp0\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { temp0[1] } "NODE_NAME" } } { "count_distance.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/count_distance/count_distance.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.483 ns) + CELL(0.414 ns) 0.897 ns LessThan0~133 2 COMB LCCOMB_X28_Y12_N0 1 " "Info: 2: + IC(0.483 ns) + CELL(0.414 ns) = 0.897 ns; Loc. = LCCOMB_X28_Y12_N0; Fanout = 1; COMB Node = 'LessThan0~133'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.897 ns" { temp0[1] LessThan0~133 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1695 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 0.968 ns LessThan0~135 3 COMB LCCOMB_X28_Y12_N2 1 " "Info: 3: + IC(0.000 ns) + CELL(0.071 ns) = 0.968 ns; Loc. = LCCOMB_X28_Y12_N2; Fanout = 1; COMB Node = 'LessThan0~135'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { LessThan0~133 LessThan0~135 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1695 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.039 ns LessThan0~137 4 COMB LCCOMB_X28_Y12_N4 1 " "Info: 4: + IC(0.000 ns) + CELL(0.071 ns) = 1.039 ns; Loc. = LCCOMB_X28_Y12_N4; Fanout = 1; COMB Node = 'LessThan0~137'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { LessThan0~135 LessThan0~137 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1695 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.110 ns LessThan0~139 5 COMB LCCOMB_X28_Y12_N6 1 " "Info: 5: + IC(0.000 ns) + CELL(0.071 ns) = 1.110 ns; Loc. = LCCOMB_X28_Y12_N6; Fanout = 1; COMB Node = 'LessThan0~139'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { LessThan0~137 LessThan0~139 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1695 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.181 ns LessThan0~141 6 COMB LCCOMB_X28_Y12_N8 1 " "Info: 6: + IC(0.000 ns) + CELL(0.071 ns) = 1.181 ns; Loc. = LCCOMB_X28_Y12_N8; Fanout = 1; COMB Node = 'LessThan0~141'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { LessThan0~139 LessThan0~141 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1695 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 1.591 ns LessThan0~142 7 COMB LCCOMB_X28_Y12_N10 2 " "Info: 7: + IC(0.000 ns) + CELL(0.410 ns) = 1.591 ns; Loc. = LCCOMB_X28_Y12_N10; Fanout = 2; COMB Node = 'LessThan0~142'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.410 ns" { LessThan0~141 LessThan0~142 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1695 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.250 ns) + CELL(0.150 ns) 1.991 ns LessThan0~144 8 COMB LCCOMB_X28_Y12_N12 9 " "Info: 8: + IC(0.250 ns) + CELL(0.150 ns) = 1.991 ns; Loc. = LCCOMB_X28_Y12_N12; Fanout = 9; COMB Node = 'LessThan0~144'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.400 ns" { LessThan0~142 LessThan0~144 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1695 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.228 ns) + CELL(0.660 ns) 2.879 ns temp1\[2\] 9 REG LCFF_X28_Y12_N17 3 " "Info: 9: + IC(0.228 ns) + CELL(0.660 ns) = 2.879 ns; Loc. = LCFF_X28_Y12_N17; Fanout = 3; REG Node = 'temp1\[2\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.888 ns" { LessThan0~144 temp1[2] } "NODE_NAME" } } { "count_distance.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/count_distance/count_distance.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.918 ns ( 66.62 % ) " "Info: Total cell delay = 1.918 ns ( 66.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.961 ns ( 33.38 % ) " "Info: Total interconnect delay = 0.961 ns ( 33.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.879 ns" { temp0[1] LessThan0~133 LessThan0~135 LessThan0~137 LessThan0~139 LessThan0~141 LessThan0~142 LessThan0~144 temp1[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.879 ns" { temp0[1] LessThan0~133 LessThan0~135 LessThan0~137 LessThan0~139 LessThan0~141 LessThan0~142 LessThan0~144 temp1[2] } { 0.000ns 0.483ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.250ns 0.228ns } { 0.000ns 0.414ns 0.071ns 0.071ns 0.071ns 0.071ns 0.410ns 0.150ns 0.660ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin destination 2.673 ns + Shortest register " "Info: + Shortest clock path from clock \"clkin\" to destination register is 2.673 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clkin 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clkin'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clkin } "NODE_NAME" } } { "count_distance.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/count_distance/count_distance.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clkin~clkctrl 2 COMB CLKCTRL_G3 20 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 20; COMB Node = 'clkin~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clkin clkin~clkctrl } "NODE_NAME" } } { "count_distance.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/count_distance/count_distance.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.019 ns) + CELL(0.537 ns) 2.673 ns temp1\[2\] 3 REG LCFF_X28_Y12_N17 3 " "Info: 3: + IC(1.019 ns) + CELL(0.537 ns) = 2.673 ns; Loc. = LCFF_X28_Y12_N17; Fanout = 3; REG Node = 'temp1\[2\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.556 ns" { clkin~clkctrl temp1[2] } "NODE_NAME" } } { "count_distance.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/count_distance/count_distance.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.46 % ) " "Info: Total cell delay = 1.536 ns ( 57.46 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.137 ns ( 42.54 % ) " "Info: Total interconnect delay = 1.137 ns ( 42.54 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.673 ns" { clkin clkin~clkctrl temp1[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.673 ns" { clkin clkin~combout clkin~clkctrl temp1[2] } { 0.000ns 0.000ns 0.118ns 1.019ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin source 2.673 ns - Longest register " "Info: - Longest clock path from clock \"clkin\" to source register is 2.673 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clkin 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clkin'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clkin } "NODE_NAME" } } { "count_distance.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/count_distance/count_distance.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clkin~clkctrl 2 COMB CLKCTRL_G3 20 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 20; COMB Node = 'clkin~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clkin clkin~clkctrl } "NODE_NAME" } } { "count_distance.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/count_distance/count_distance.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.019 ns) + CELL(0.537 ns) 2.673 ns temp0\[1\] 3 REG LCFF_X27_Y12_N15 5 " "Info: 3: + IC(1.019 ns) + CELL(0.537 ns) = 2.673 ns; Loc. = LCFF_X27_Y12_N15; Fanout = 5; REG Node = 'temp0\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.556 ns" { clkin~clkctrl temp0[1] } "NODE_NAME" } } { "count_distance.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/count_distance/count_distance.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.46 % ) " "Info: Total cell delay = 1.536 ns ( 57.46 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.137 ns ( 42.54 % ) " "Info: Total interconnect delay = 1.137 ns ( 42.54 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.673 ns" { clkin clkin~clkctrl temp0[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.673 ns" { clkin clkin~combout clkin~clkctrl temp0[1] } { 0.000ns 0.000ns 0.118ns 1.019ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.673 ns" { clkin clkin~clkctrl temp1[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.673 ns" { clkin clkin~combout clkin~clkctrl temp1[2] } { 0.000ns 0.000ns 0.118ns 1.019ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.673 ns" { clkin clkin~clkctrl temp0[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.673 ns" { clkin clkin~combout clkin~clkctrl temp0[1] } { 0.000ns 0.000ns 0.118ns 1.019ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "count_distance.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/count_distance/count_distance.vhd" 27 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "count_distance.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/count_distance/count_distance.vhd" 34 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.879 ns" { temp0[1] LessThan0~133 LessThan0~135 LessThan0~137 LessThan0~139 LessThan0~141 LessThan0~142 LessThan0~144 temp1[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.879 ns" { temp0[1] LessThan0~133 LessThan0~135 LessThan0~137 LessThan0~139 LessThan0~141 LessThan0~142 LessThan0~144 temp1[2] } { 0.000ns 0.483ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.250ns 0.228ns } { 0.000ns 0.414ns 0.071ns 0.071ns 0.071ns 0.071ns 0.410ns 0.150ns 0.660ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.673 ns" { clkin clkin~clkctrl temp1[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.673 ns" { clkin clkin~combout clkin~clkctrl temp1[2] } { 0.000ns 0.000ns 0.118ns 1.019ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.673 ns" { clkin clkin~clkctrl temp0[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.673 ns" { clkin clkin~combout clkin~clkctrl temp0[1] } { 0.000ns 0.000ns 0.118ns 1.019ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "temp1\[2\] dip\[0\] clkin 7.226 ns register " "Info: tsu for register \"temp1\[2\]\" (data pin = \"dip\[0\]\", clock pin = \"clkin\") is 7.226 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.935 ns + Longest pin register " "Info: + Longest pin to register delay is 9.935 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.842 ns) 0.842 ns dip\[0\] 1 PIN PIN_U9 7 " "Info: 1: + IC(0.000 ns) + CELL(0.842 ns) = 0.842 ns; Loc. = PIN_U9; Fanout = 7; PIN Node = 'dip\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { dip[0] } "NODE_NAME" } } { "count_distance.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/count_distance/count_distance.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.625 ns) + CELL(0.438 ns) 6.905 ns Mux4~12 2 COMB LCCOMB_X29_Y12_N8 3 " "Info: 2: + IC(5.625 ns) + CELL(0.438 ns) = 6.905 ns; Loc. = LCCOMB_X29_Y12_N8; Fanout = 3; COMB Node = 'Mux4~12'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.063 ns" { dip[0] Mux4~12 } "NODE_NAME" } } { "count_distance.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/count_distance/count_distance.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.705 ns) + CELL(0.414 ns) 8.024 ns LessThan0~135 3 COMB LCCOMB_X28_Y12_N2 1 " "Info: 3: + IC(0.705 ns) + CELL(0.414 ns) = 8.024 ns; Loc. = LCCOMB_X28_Y12_N2; Fanout = 1; COMB Node = 'LessThan0~135'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.119 ns" { Mux4~12 LessThan0~135 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1695 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 8.095 ns LessThan0~137 4 COMB LCCOMB_X28_Y12_N4 1 " "Info: 4: + IC(0.000 ns) + CELL(0.071 ns) = 8.095 ns; Loc. = LCCOMB_X28_Y12_N4; Fanout = 1; COMB Node = 'LessThan0~137'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { LessThan0~135 LessThan0~137 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1695 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 8.166 ns LessThan0~139 5 COMB LCCOMB_X28_Y12_N6 1 " "Info: 5: + IC(0.000 ns) + CELL(0.071 ns) = 8.166 ns; Loc. = LCCOMB_X28_Y12_N6; Fanout = 1; COMB Node = 'LessThan0~139'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { LessThan0~137 LessThan0~139 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1695 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 8.237 ns LessThan0~141 6 COMB LCCOMB_X28_Y12_N8 1 " "Info: 6: + IC(0.000 ns) + CELL(0.071 ns) = 8.237 ns; Loc. = LCCOMB_X28_Y12_N8; Fanout = 1; COMB Node = 'LessThan0~141'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { LessThan0~139 LessThan0~141 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1695 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 8.647 ns LessThan0~142 7 COMB LCCOMB_X28_Y12_N10 2 " "Info: 7: + IC(0.000 ns) + CELL(0.410 ns) = 8.647 ns; Loc. = LCCOMB_X28_Y12_N10; Fanout = 2; COMB Node = 'LessThan0~142'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.410 ns" { LessThan0~141 LessThan0~142 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1695 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.250 ns) + CELL(0.150 ns) 9.047 ns LessThan0~144 8 COMB LCCOMB_X28_Y12_N12 9 " "Info: 8: + IC(0.250 ns) + CELL(0.150 ns) = 9.047 ns; Loc. = LCCOMB_X28_Y12_N12; Fanout = 9; COMB Node = 'LessThan0~144'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.400 ns" { LessThan0~142 LessThan0~144 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1695 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.228 ns) + CELL(0.660 ns) 9.935 ns temp1\[2\] 9 REG LCFF_X28_Y12_N17 3 " "Info: 9: + IC(0.228 ns) + CELL(0.660 ns) = 9.935 ns; Loc. = LCFF_X28_Y12_N17; Fanout = 3; REG Node = 'temp1\[2\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.888 ns" { LessThan0~144 temp1[2] } "NODE_NAME" } } { "count_distance.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/count_distance/count_distance.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.127 ns ( 31.47 % ) " "Info: Total cell delay = 3.127 ns ( 31.47 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.808 ns ( 68.53 % ) " "Info: Total interconnect delay = 6.808 ns ( 68.53 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.935 ns" { dip[0] Mux4~12 LessThan0~135 LessThan0~137 LessThan0~139 LessThan0~141 LessThan0~142 LessThan0~144 temp1[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "9.935 ns" { dip[0] dip[0]~combout Mux4~12 LessThan0~135 LessThan0~137 LessThan0~139 LessThan0~141 LessThan0~142 LessThan0~144 temp1[2] } { 0.000ns 0.000ns 5.625ns 0.705ns 0.000ns 0.000ns 0.000ns 0.000ns 0.250ns 0.228ns } { 0.000ns 0.842ns 0.438ns 0.414ns 0.071ns 0.071ns 0.071ns 0.410ns 0.150ns 0.660ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "count_distance.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/count_distance/count_distance.vhd" 34 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin destination 2.673 ns - Shortest register " "Info: - Shortest clock path from clock \"clkin\" to destination register is 2.673 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clkin 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clkin'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clkin } "NODE_NAME" } } { "count_distance.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/count_distance/count_distance.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clkin~clkctrl 2 COMB CLKCTRL_G3 20 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 20; COMB Node = 'clkin~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clkin clkin~clkctrl } "NODE_NAME" } } { "count_distance.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/count_distance/count_distance.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.019 ns) + CELL(0.537 ns) 2.673 ns temp1\[2\] 3 REG LCFF_X28_Y12_N17 3 " "Info: 3: + IC(1.019 ns) + CELL(0.537 ns) = 2.673 ns; Loc. = LCFF_X28_Y12_N17; Fanout = 3; REG Node = 'temp1\[2\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.556 ns" { clkin~clkctrl temp1[2] } "NODE_NAME" } } { "count_distance.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/count_distance/count_distance.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.46 % ) " "Info: Total cell delay = 1.536 ns ( 57.46 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.137 ns ( 42.54 % ) " "Info: Total interconnect delay = 1.137 ns ( 42.54 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.673 ns" { clkin clkin~clkctrl temp1[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.673 ns" { clkin clkin~combout clkin~clkctrl temp1[2] } { 0.000ns 0.000ns 0.118ns 1.019ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.935 ns" { dip[0] Mux4~12 LessThan0~135 LessThan0~137 LessThan0~139 LessThan0~141 LessThan0~142 LessThan0~144 temp1[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "9.935 ns" { dip[0] dip[0]~combout Mux4~12 LessThan0~135 LessThan0~137 LessThan0~139 LessThan0~141 LessThan0~142 LessThan0~144 temp1[2] } { 0.000ns 0.000ns 5.625ns 0.705ns 0.000ns 0.000ns 0.000ns 0.000ns 0.250ns 0.228ns } { 0.000ns 0.842ns 0.438ns 0.414ns 0.071ns 0.071ns 0.071ns 0.410ns 0.150ns 0.660ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.673 ns" { clkin clkin~clkctrl temp1[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.673 ns" { clkin clkin~combout clkin~clkctrl temp1[2] } { 0.000ns 0.000ns 0.118ns 1.019ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
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