count_distance.tan.rpt

基于fpga的出租车计费系统

; N/A   ; None              ; 10.616 ns       ; dip[1] ; length[3] ;
; N/A   ; None              ; 10.602 ns       ; dip[2] ; length[3] ;
; N/A   ; None              ; 10.093 ns       ; dip[1] ; length[6] ;
; N/A   ; None              ; 10.086 ns       ; dip[1] ; length[4] ;
; N/A   ; None              ; 10.079 ns       ; dip[2] ; length[6] ;
; N/A   ; None              ; 10.072 ns       ; dip[2] ; length[4] ;
; N/A   ; None              ; 9.808 ns        ; dip[1] ; length[0] ;
; N/A   ; None              ; 9.794 ns        ; dip[2] ; length[0] ;
+-------+-------------------+-----------------+--------+-----------+


+------------------------------------------------------------------------+
; th                                                                     ;
+---------------+-------------+-----------+--------+----------+----------+
; Minimum Slack ; Required th ; Actual th ; From   ; To       ; To Clock ;
+---------------+-------------+-----------+--------+----------+----------+
; N/A           ; None        ; -1.922 ns ; dip[1] ; temp1[0] ; clkin    ;
; N/A           ; None        ; -2.269 ns ; dip[2] ; temp1[0] ; clkin    ;
; N/A           ; None        ; -2.531 ns ; dip[1] ; temp1[2] ; clkin    ;
; N/A           ; None        ; -2.531 ns ; dip[1] ; temp1[9] ; clkin    ;
; N/A           ; None        ; -2.531 ns ; dip[1] ; temp1[1] ; clkin    ;
; N/A           ; None        ; -2.531 ns ; dip[1] ; temp1[5] ; clkin    ;
; N/A           ; None        ; -2.531 ns ; dip[1] ; temp1[6] ; clkin    ;
; N/A           ; None        ; -2.531 ns ; dip[1] ; temp1[8] ; clkin    ;
; N/A           ; None        ; -2.531 ns ; dip[1] ; temp1[7] ; clkin    ;
; N/A           ; None        ; -2.531 ns ; dip[1] ; temp1[4] ; clkin    ;
; N/A           ; None        ; -2.531 ns ; dip[1] ; temp1[3] ; clkin    ;
; N/A           ; None        ; -2.878 ns ; dip[2] ; temp1[2] ; clkin    ;
; N/A           ; None        ; -2.878 ns ; dip[2] ; temp1[9] ; clkin    ;
; N/A           ; None        ; -2.878 ns ; dip[2] ; temp1[1] ; clkin    ;
; N/A           ; None        ; -2.878 ns ; dip[2] ; temp1[5] ; clkin    ;
; N/A           ; None        ; -2.878 ns ; dip[2] ; temp1[6] ; clkin    ;
; N/A           ; None        ; -2.878 ns ; dip[2] ; temp1[8] ; clkin    ;
; N/A           ; None        ; -2.878 ns ; dip[2] ; temp1[7] ; clkin    ;
; N/A           ; None        ; -2.878 ns ; dip[2] ; temp1[4] ; clkin    ;
; N/A           ; None        ; -2.878 ns ; dip[2] ; temp1[3] ; clkin    ;
; N/A           ; None        ; -5.487 ns ; dip[0] ; temp1[0] ; clkin    ;
; N/A           ; None        ; -6.096 ns ; dip[0] ; temp1[2] ; clkin    ;
; N/A           ; None        ; -6.096 ns ; dip[0] ; temp1[9] ; clkin    ;
; N/A           ; None        ; -6.096 ns ; dip[0] ; temp1[1] ; clkin    ;
; N/A           ; None        ; -6.096 ns ; dip[0] ; temp1[5] ; clkin    ;
; N/A           ; None        ; -6.096 ns ; dip[0] ; temp1[6] ; clkin    ;
; N/A           ; None        ; -6.096 ns ; dip[0] ; temp1[8] ; clkin    ;
; N/A           ; None        ; -6.096 ns ; dip[0] ; temp1[7] ; clkin    ;
; N/A           ; None        ; -6.096 ns ; dip[0] ; temp1[4] ; clkin    ;
; N/A           ; None        ; -6.096 ns ; dip[0] ; temp1[3] ; clkin    ;
+---------------+-------------+-----------+--------+----------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Wed Oct 08 11:35:10 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off count_distance -c count_distance --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clkin" is an undefined clock
Info: Clock "clkin" has Internal fmax of 323.31 MHz between source register "temp0[1]" and destination register "temp1[2]" (period= 3.093 ns)
    Info: + Longest register to register delay is 2.879 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X27_Y12_N15; Fanout = 5; REG Node = 'temp0[1]'
        Info: 2: + IC(0.483 ns) + CELL(0.414 ns) = 0.897 ns; Loc. = LCCOMB_X28_Y12_N0; Fanout = 1; COMB Node = 'LessThan0~133'
        Info: 3: + IC(0.000 ns) + CELL(0.071 ns) = 0.968 ns; Loc. = LCCOMB_X28_Y12_N2; Fanout = 1; COMB Node = 'LessThan0~135'
        Info: 4: + IC(0.000 ns) + CELL(0.071 ns) = 1.039 ns; Loc. = LCCOMB_X28_Y12_N4; Fanout = 1; COMB Node = 'LessThan0~137'
        Info: 5: + IC(0.000 ns) + CELL(0.071 ns) = 1.110 ns; Loc. = LCCOMB_X28_Y12_N6; Fanout = 1; COMB Node = 'LessThan0~139'
        Info: 6: + IC(0.000 ns) + CELL(0.071 ns) = 1.181 ns; Loc. = LCCOMB_X28_Y12_N8; Fanout = 1; COMB Node = 'LessThan0~141'
        Info: 7: + IC(0.000 ns) + CELL(0.410 ns) = 1.591 ns; Loc. = LCCOMB_X28_Y12_N10; Fanout = 2; COMB Node = 'LessThan0~142'
        Info: 8: + IC(0.250 ns) + CELL(0.150 ns) = 1.991 ns; Loc. = LCCOMB_X28_Y12_N12; Fanout = 9; COMB Node = 'LessThan0~144'
        Info: 9: + IC(0.228 ns) + CELL(0.660 ns) = 2.879 ns; Loc. = LCFF_X28_Y12_N17; Fanout = 3; REG Node = 'temp1[2]'
        Info: Total cell delay = 1.918 ns ( 66.62 % )
        Info: Total interconnect delay = 0.961 ns ( 33.38 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clkin" to destination register is 2.673 ns
            Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clkin'
            Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 20; COMB Node = 'clkin~clkctrl'
            Info: 3: + IC(1.019 ns) + CELL(0.537 ns) = 2.673 ns; Loc. = LCFF_X28_Y12_N17; Fanout = 3; REG Node = 'temp1[2]'
            Info: Total cell delay = 1.536 ns ( 57.46 % )
            Info: Total interconnect delay = 1.137 ns ( 42.54 % )
        Info: - Longest clock path from clock "clkin" to source register is 2.673 ns
            Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clkin'
            Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 20; COMB Node = 'clkin~clkctrl'
            Info: 3: + IC(1.019 ns) + CELL(0.537 ns) = 2.673 ns; Loc. = LCFF_X27_Y12_N15; Fanout = 5; REG Node = 'temp0[1]'
            Info: Total cell delay = 1.536 ns ( 57.46 % )
            Info: Total interconnect delay = 1.137 ns ( 42.54 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Micro setup delay of destination is -0.036 ns
Info: tsu for register "temp1[2]" (data pin = "dip[0]", clock pin = "clkin") is 7.226 ns
    Info: + Longest pin to register delay is 9.935 ns
        Info: 1: + IC(0.000 ns) + CELL(0.842 ns) = 0.842 ns; Loc. = PIN_U9; Fanout = 7; PIN Node = 'dip[0]'
        Info: 2: + IC(5.625 ns) + CELL(0.438 ns) = 6.905 ns; Loc. = LCCOMB_X29_Y12_N8; Fanout = 3; COMB Node = 'Mux4~12'
        Info: 3: + IC(0.705 ns) + CELL(0.414 ns) = 8.024 ns; Loc. = LCCOMB_X28_Y12_N2; Fanout = 1; COMB Node = 'LessThan0~135'
        Info: 4: + IC(0.000 ns) + CELL(0.071 ns) = 8.095 ns; Loc. = LCCOMB_X28_Y12_N4; Fanout = 1; COMB Node = 'LessThan0~137'
        Info: 5: + IC(0.000 ns) + CELL(0.071 ns) = 8.166 ns; Loc. = LCCOMB_X28_Y12_N6; Fanout = 1; COMB Node = 'LessThan0~139'
        Info: 6: + IC(0.000 ns) + CELL(0.071 ns) = 8.237 ns; Loc. = LCCOMB_X28_Y12_N8; Fanout = 1; COMB Node = 'LessThan0~141'
        Info: 7: + IC(0.000 ns) + CELL(0.410 ns) = 8.647 ns; Loc. = LCCOMB_X28_Y12_N10; Fanout = 2; COMB Node = 'LessThan0~142'
        Info: 8: + IC(0.250 ns) + CELL(0.150 ns) = 9.047 ns; Loc. = LCCOMB_X28_Y12_N12; Fanout = 9; COMB Node = 'LessThan0~144'
        Info: 9: + IC(0.228 ns) + CELL(0.660 ns) = 9.935 ns; Loc. = LCFF_X28_Y12_N17; Fanout = 3; REG Node = 'temp1[2]'
        Info: Total cell delay = 3.127 ns ( 31.47 % )
        Info: Total interconnect delay = 6.808 ns ( 68.53 % )
    Info: + Micro setup delay of destination is -0.036 ns
    Info: - Shortest clock path from clock "clkin" to destination register is 2.673 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clkin'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 20; COMB Node = 'clkin~clkctrl'
        Info: 3: + IC(1.019 ns) + CELL(0.537 ns) = 2.673 ns; Loc. = LCFF_X28_Y12_N17; Fanout = 3; REG Node = 'temp1[2]'
        Info: Total cell delay = 1.536 ns ( 57.46 % )
        Info: Total interconnect delay = 1.137 ns ( 42.54 % )
Info: tco from clock "clkin" to destination pin "length[5]" through register "temp0[0]" is 11.416 ns
    Info: + Longest clock path from clock "clkin" to source register is 2.666 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc.