count_money.tan.qmsg

基于fpga的出租车计费系统

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clkin " "Info: Assuming node \"clkin\" is an undefined clock" {  } { { "count_money.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/count_money/count_money.vhd" 7 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clkin" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clkin register register temp0\[1\] temp0\[9\] 420.17 MHz Internal " "Info: Clock \"clkin\" Internal fmax is restricted to 420.17 MHz between source register \"temp0\[1\]\" and destination register \"temp0\[9\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.38 ns " "Info: fmax restricted to clock pin edge rate 2.38 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.826 ns + Longest register register " "Info: + Longest register to register delay is 1.826 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns temp0\[1\] 1 REG LCFF_X29_Y35_N11 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X29_Y35_N11; Fanout = 4; REG Node = 'temp0\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { temp0[1] } "NODE_NAME" } } { "count_money.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/count_money/count_money.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.333 ns) + CELL(0.414 ns) 0.747 ns temp0\[1\]~95 2 COMB LCCOMB_X29_Y35_N10 2 " "Info: 2: + IC(0.333 ns) + CELL(0.414 ns) = 0.747 ns; Loc. = LCCOMB_X29_Y35_N10; Fanout = 2; COMB Node = 'temp0\[1\]~95'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.747 ns" { temp0[1] temp0[1]~95 } "NODE_NAME" } } { "count_money.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/count_money/count_money.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 0.818 ns temp0\[2\]~96 3 COMB LCCOMB_X29_Y35_N12 2 " "Info: 3: + IC(0.000 ns) + CELL(0.071 ns) = 0.818 ns; Loc. = LCCOMB_X29_Y35_N12; Fanout = 2; COMB Node = 'temp0\[2\]~96'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { temp0[1]~95 temp0[2]~96 } "NODE_NAME" } } { "count_money.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/count_money/count_money.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.159 ns) 0.977 ns temp0\[3\]~97 4 COMB LCCOMB_X29_Y35_N14 2 " "Info: 4: + IC(0.000 ns) + CELL(0.159 ns) = 0.977 ns; Loc. = LCCOMB_X29_Y35_N14; Fanout = 2; COMB Node = 'temp0\[3\]~97'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.159 ns" { temp0[2]~96 temp0[3]~97 } "NODE_NAME" } } { "count_money.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/count_money/count_money.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.048 ns temp0\[4\]~98 5 COMB LCCOMB_X29_Y35_N16 2 " "Info: 5: + IC(0.000 ns) + CELL(0.071 ns) = 1.048 ns; Loc. = LCCOMB_X29_Y35_N16; Fanout = 2; COMB Node = 'temp0\[4\]~98'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { temp0[3]~97 temp0[4]~98 } "NODE_NAME" } } { "count_money.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/count_money/count_money.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.119 ns temp0\[5\]~99 6 COMB LCCOMB_X29_Y35_N18 2 " "Info: 6: + IC(0.000 ns) + CELL(0.071 ns) = 1.119 ns; Loc. = LCCOMB_X29_Y35_N18; Fanout = 2; COMB Node = 'temp0\[5\]~99'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { temp0[4]~98 temp0[5]~99 } "NODE_NAME" } } { "count_money.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/count_money/count_money.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.190 ns temp0\[6\]~100 7 COMB LCCOMB_X29_Y35_N20 2 " "Info: 7: + IC(0.000 ns) + CELL(0.071 ns) = 1.190 ns; Loc. = LCCOMB_X29_Y35_N20; Fanout = 2; COMB Node = 'temp0\[6\]~100'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { temp0[5]~99 temp0[6]~100 } "NODE_NAME" } } { "count_money.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/count_money/count_money.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.261 ns temp0\[7\]~101 8 COMB LCCOMB_X29_Y35_N22 2 " "Info: 8: + IC(0.000 ns) + CELL(0.071 ns) = 1.261 ns; Loc. = LCCOMB_X29_Y35_N22; Fanout = 2; COMB Node = 'temp0\[7\]~101'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { temp0[6]~100 temp0[7]~101 } "NODE_NAME" } } { "count_money.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/count_money/count_money.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.332 ns temp0\[8\]~102 9 COMB LCCOMB_X29_Y35_N24 1 " "Info: 9: + IC(0.000 ns) + CELL(0.071 ns) = 1.332 ns; Loc. = LCCOMB_X29_Y35_N24; Fanout = 1; COMB Node = 'temp0\[8\]~102'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { temp0[7]~101 temp0[8]~102 } "NODE_NAME" } } { "count_money.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/count_money/count_money.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 1.742 ns temp0\[9\]~43 10 COMB LCCOMB_X29_Y35_N26 1 " "Info: 10: + IC(0.000 ns) + CELL(0.410 ns) = 1.742 ns; Loc. = LCCOMB_X29_Y35_N26; Fanout = 1; COMB Node = 'temp0\[9\]~43'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.410 ns" { temp0[8]~102 temp0[9]~43 } "NODE_NAME" } } { "count_money.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/count_money/count_money.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 1.826 ns temp0\[9\] 11 REG LCFF_X29_Y35_N27 3 " "Info: 11: + IC(0.000 ns) + CELL(0.084 ns) = 1.826 ns; Loc. = LCFF_X29_Y35_N27; Fanout = 3; REG Node = 'temp0\[9\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { temp0[9]~43 temp0[9] } "NODE_NAME" } } { "count_money.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/count_money/count_money.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.493 ns ( 81.76 % ) " "Info: Total cell delay = 1.493 ns ( 81.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.333 ns ( 18.24 % ) " "Info: Total interconnect delay = 0.333 ns ( 18.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.826 ns" { temp0[1] temp0[1]~95 temp0[2]~96 temp0[3]~97 temp0[4]~98 temp0[5]~99 temp0[6]~100 temp0[7]~101 temp0[8]~102 temp0[9]~43 temp0[9] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "1.826 ns" { temp0[1] temp0[1]~95 temp0[2]~96 temp0[3]~97 temp0[4]~98 temp0[5]~99 temp0[6]~100 temp0[7]~101 temp0[8]~102 temp0[9]~43 temp0[9] } { 0.000ns 0.333ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.414ns 0.071ns 0.159ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.410ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin destination 2.697 ns + Shortest register " "Info: + Shortest clock path from clock \"clkin\" to destination register is 2.697 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clkin 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clkin'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clkin } "NODE_NAME" } } { "count_money.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/count_money/count_money.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clkin~clkctrl 2 COMB CLKCTRL_G3 10 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 10; COMB Node = 'clkin~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clkin clkin~clkctrl } "NODE_NAME" } } { "count_money.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/count_money/count_money.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.043 ns) + CELL(0.537 ns) 2.697 ns temp0\[9\] 3 REG LCFF_X29_Y35_N27 3 " "Info: 3: + IC(1.043 ns) + CELL(0.537 ns) = 2.697 ns; Loc. = LCFF_X29_Y35_N27; Fanout = 3; REG Node = 'temp0\[9\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.580 ns" { clkin~clkctrl temp0[9] } "NODE_NAME" } } { "count_money.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/count_money/count_money.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 56.95 % ) " "Info: Total cell delay = 1.536 ns ( 56.95 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.161 ns ( 43.05 % ) " "Info: Total interconnect delay = 1.161 ns ( 43.05 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.697 ns" { clkin clkin~clkctrl temp0[9] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.697 ns" { clkin clkin~combout clkin~clkctrl temp0[9] } { 0.000ns 0.000ns 0.118ns 1.043ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin source 2.697 ns - Longest register " "Info: - Longest clock path from clock \"clkin\" to source register is 2.697 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clkin 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clkin'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clkin } "NODE_NAME" } } { "count_money.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/count_money/count_money.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clkin~clkctrl 2 COMB CLKCTRL_G3 10 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 10; COMB Node = 'clkin~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clkin clkin~clkctrl } "NODE_NAME" } } { "count_money.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/count_money/count_money.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.043 ns) + CELL(0.537 ns) 2.697 ns temp0\[1\] 3 REG LCFF_X29_Y35_N11 4 " "Info: 3: + IC(1.043 ns) + CELL(0.537 ns) = 2.697 ns; Loc. = LCFF_X29_Y35_N11; Fanout = 4; REG Node = 'temp0\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.580 ns" { clkin~clkctrl temp0[1] } "NODE_NAME" } } { "count_money.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/count_money/count_money.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 56.95 % ) " "Info: Total cell delay = 1.536 ns ( 56.95 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.161 ns ( 43.05 % ) " "Info: Total interconnect delay = 1.161 ns ( 43.05 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.697 ns" { clkin clkin~clkctrl temp0[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.697 ns" { clkin clkin~combout clkin~clkctrl temp0[1] } { 0.000ns 0.000ns 0.118ns 1.043ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.697 ns" { clkin clkin~clkctrl temp0[9] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.697 ns" { clkin clkin~combout clkin~clkctrl temp0[9] } { 0.000ns 0.000ns 0.118ns 1.043ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.697 ns" { clkin clkin~clkctrl temp0[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.697 ns" { clkin clkin~combout clkin~clkctrl temp0[1] } { 0.000ns 0.000ns 0.118ns 1.043ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "count_money.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/count_money/count_money.vhd" 22 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "count_money.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/count_money/count_money.vhd" 22 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.826 ns" { temp0[1] temp0[1]~95 temp0[2]~96 temp0[3]~97 temp0[4]~98 temp0[5]~99 temp0[6]~100 temp0[7]~101 temp0[8]~102 temp0[9]~43 temp0[9] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "1.826 ns" { temp0[1] temp0[1]~95 temp0[2]~96 temp0[3]~97 temp0[4]~98 temp0[5]~99 temp0[6]~100 temp0[7]~101 temp0[8]~102 temp0[9]~43 temp0[9] } { 0.000ns 0.333ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.414ns 0.071ns 0.159ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.410ns 0.084ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.697 ns" { clkin clkin~clkctrl temp0[9] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.697 ns" { clkin clkin~combout clkin~clkctrl temp0[9] } { 0.000ns 0.000ns 0.118ns 1.043ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.697 ns" { clkin clkin~clkctrl temp0[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.697 ns" { clkin clkin~combout clkin~clkctrl temp0[1] } { 0.000ns 0.000ns 0.118ns 1.043ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { temp0[9] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { temp0[9] } {  } {  } } } { "count_money.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/count_money/count_money.vhd" 22 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clkin money\[3\] temp0\[0\] 10.829 ns register " "Info: tco from clock \"clkin\" to destination pin \"money\[3\]\" through register \"temp0\[0\]\" is 10.829 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin source 2.697 ns + Longest register " "Info: + Longest clock path from clock \"clkin\" to source register is 2.697 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clkin 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clkin'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clkin } "NODE_NAME" } } { "count_money.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/count_money/count_money.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clkin~clkctrl 2 COMB CLKCTRL_G3 10 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 10; COMB Node = 'clkin~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clkin clkin~clkctrl } "NODE_NAME" } } { "count_money.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/count_money/count_money.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.043 ns) + CELL(0.537 ns) 2.697 ns temp0\[0\] 3 REG LCFF_X29_Y35_N5 5 " "Info: 3: + IC(1.043 ns) + CELL(0.537 ns) = 2.697 ns; Loc. = LCFF_X29_Y35_N5; Fanout = 5; REG Node = 'temp0\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.580 ns" { clkin~clkctrl temp0[0] } "NODE_NAME" } } { "count_money.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/count_money/count_money.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 56.95 % ) " "Info: Total cell delay = 1.536 ns ( 56.95 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.161 ns ( 43.05 % ) " "Info: Total interconnect delay = 1.161 ns ( 43.05 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.697 ns" { clkin clkin~clkctrl temp0[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.697 ns" { clkin clkin~combout clkin~clkctrl temp0[0] } { 0.000ns 0.000ns 0.118ns 1.043ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "count_money.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/count_money/count_money.vhd" 22 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.882 ns + Longest register pin " "Info: + Longest register to pin delay is 7.882 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns temp0\[0\] 1 REG LCFF_X29_Y35_N5 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X29_Y35_N5; Fanout = 5; REG Node = 'temp0\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { temp0[0] } "NODE_NAME" } } { "count_money.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/count_money/count_money.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.504 ns) + CELL(0.437 ns) 0.941 ns LessThan0~350 2 COMB LCCOMB_X29_Y35_N2 1 " "Info: 2: + IC(0.504 ns) + CELL(0.437 ns) = 0.941 ns; Loc. = LCCOMB_X29_Y35_N2; Fanout = 1; COMB Node = 'LessThan0~350'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.941 ns" { temp0[0] LessThan0~350 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1547 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.246 ns) + CELL(0.150 ns) 1.337 ns LessThan0~351 3 COMB LCCOMB_X29_Y35_N6 1 " "Info: 3: + IC(0.246 ns) + CELL(0.150 ns) = 1.337 ns; Loc. = LCCOMB_X29_Y35_N6; Fanout = 1; COMB Node = 'LessThan0~351'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.396 ns" { LessThan0~350 LessThan0~351 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1547 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.267 ns) + CELL(0.438 ns) 2.042 ns LessThan0~352 4 COMB LCCOMB_X29_Y35_N0 4 " "Info: 4: + IC(0.267 ns) + CELL(0.438 ns) = 2.042 ns; Loc. = LCCOMB_X29_Y35_N0; Fanout = 4; COMB Node = 'LessThan0~352'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.705 ns" { LessThan0~351 LessThan0~352 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1547 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.451 ns) + CELL(0.275 ns) 2.768 ns money~454 5 COMB LCCOMB_X30_Y35_N16 1 " "Info: 5: + IC(0.451 ns) + CELL(0.275 ns) = 2.768 ns; Loc. = LCCOMB_X30_Y35_N16; Fanout = 1; COMB Node = 'money~454'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.726 ns" { LessThan0~352 money~454 } "NODE_NAME" } } { "count_money.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/count_money/count_money.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.472 ns) + CELL(2.642 ns) 7.882 ns money\[3\] 6 PIN PIN_D23 0 " "Info: 6: + IC(2.472 ns) + CELL(2.642 ns) = 7.882 ns; Loc. = PIN_D23; Fanout = 0; PIN Node = 'money\[3\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.114 ns" { money~454 money[3] } "NODE_NAME" } } { "count_money.vhd" "" { Text "E:/SOPClab/digital_system_design/texi_jifei_system/count_money/count_money.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.942 ns ( 50.01 % ) " "Info: Total cell delay = 3.942 ns ( 50.01 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.940 ns ( 49.99 % ) " "Info: Total interconnect delay = 3.940 ns ( 49.99 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.882 ns" { temp0[0] LessThan0~350 LessThan0~351 LessThan0~352 money~454 money[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.882 ns" { temp0[0] LessThan0~350 LessThan0~351 LessThan0~352 money~454 money[3] } { 0.000ns 0.504ns 0.246ns 0.267ns 0.451ns 2.472ns } { 0.000ns 0.437ns 0.150ns 0.438ns 0.275ns 2.642ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.697 ns" { clkin clkin~clkctrl temp0[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.697 ns" { clkin clkin~combout clkin~clkctrl temp0[0] } { 0.000ns 0.000ns 0.118ns 1.043ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.882 ns" { temp0[0] LessThan0~350 LessThan0~351 LessThan0~352 money~454 money[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.882 ns" { temp0[0] LessThan0~350 LessThan0~351 LessThan0~352 money~454 money[3] } { 0.000ns 0.504ns 0.246ns 0.267ns 0.451ns 2.472ns } { 0.000ns 0.437ns 0.150ns 0.438ns 0.275ns 2.642ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}