📄 openlock.tan.qmsg

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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register temp4\[2\] register lockopen~reg0 375.8 MHz 2.661 ns Internal " "Info: Clock \"clk\" has Internal fmax of 375.8 MHz between source register \"temp4\[2\]\" and destination register \"lockopen~reg0\" (period= 2.661 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.447 ns + Longest register register " "Info: + Longest register to register delay is 2.447 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns temp4\[2\] 1 REG LCFF_X28_Y35_N3 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X28_Y35_N3; Fanout = 1; REG Node = 'temp4\[2\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { temp4[2] } "NODE_NAME" } } { "openlock.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/openlock/openlock.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.301 ns) + CELL(0.150 ns) 0.451 ns lockopen~293 2 COMB LCCOMB_X28_Y35_N16 1 " "Info: 2: + IC(0.301 ns) + CELL(0.150 ns) = 0.451 ns; Loc. = LCCOMB_X28_Y35_N16; Fanout = 1; COMB Node = 'lockopen~293'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.451 ns" { temp4[2] lockopen~293 } "NODE_NAME" } } { "openlock.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/openlock/openlock.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.459 ns) + CELL(0.410 ns) 1.320 ns lockopen~295 3 COMB LCCOMB_X27_Y35_N14 1 " "Info: 3: + IC(0.459 ns) + CELL(0.410 ns) = 1.320 ns; Loc. = LCCOMB_X27_Y35_N14; Fanout = 1; COMB Node = 'lockopen~295'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.869 ns" { lockopen~293 lockopen~295 } "NODE_NAME" } } { "openlock.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/openlock/openlock.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.253 ns) + CELL(0.393 ns) 1.966 ns lockopen~305 4 COMB LCCOMB_X27_Y35_N10 1 " "Info: 4: + IC(0.253 ns) + CELL(0.393 ns) = 1.966 ns; Loc. = LCCOMB_X27_Y35_N10; Fanout = 1; COMB Node = 'lockopen~305'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.646 ns" { lockopen~295 lockopen~305 } "NODE_NAME" } } { "openlock.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/openlock/openlock.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.247 ns) + CELL(0.150 ns) 2.363 ns lockopen~306 5 COMB LCCOMB_X27_Y35_N0 1 " "Info: 5: + IC(0.247 ns) + CELL(0.150 ns) = 2.363 ns; Loc. = LCCOMB_X27_Y35_N0; Fanout = 1; COMB Node = 'lockopen~306'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.397 ns" { lockopen~305 lockopen~306 } "NODE_NAME" } } { "openlock.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/openlock/openlock.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 2.447 ns lockopen~reg0 6 REG LCFF_X27_Y35_N1 3 " "Info: 6: + IC(0.000 ns) + CELL(0.084 ns) = 2.447 ns; Loc. = LCFF_X27_Y35_N1; Fanout = 3; REG Node = 'lockopen~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { lockopen~306 lockopen~reg0 } "NODE_NAME" } } { "openlock.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/openlock/openlock.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.187 ns ( 48.51 % ) " "Info: Total cell delay = 1.187 ns ( 48.51 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.260 ns ( 51.49 % ) " "Info: Total interconnect delay = 1.260 ns ( 51.49 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.447 ns" { temp4[2] lockopen~293 lockopen~295 lockopen~305 lockopen~306 lockopen~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.447 ns" { temp4[2] lockopen~293 lockopen~295 lockopen~305 lockopen~306 lockopen~reg0 } { 0.000ns 0.301ns 0.459ns 0.253ns 0.247ns 0.000ns } { 0.000ns 0.150ns 0.410ns 0.393ns 0.150ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.697 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.697 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "openlock.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/openlock/openlock.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G3 25 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 25; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "openlock.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/openlock/openlock.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.043 ns) + CELL(0.537 ns) 2.697 ns lockopen~reg0 3 REG LCFF_X27_Y35_N1 3 " "Info: 3: + IC(1.043 ns) + CELL(0.537 ns) = 2.697 ns; Loc. = LCFF_X27_Y35_N1; Fanout = 3; REG Node = 'lockopen~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.580 ns" { clk~clkctrl lockopen~reg0 } "NODE_NAME" } } { "openlock.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/openlock/openlock.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 56.95 % ) " "Info: Total cell delay = 1.536 ns ( 56.95 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.161 ns ( 43.05 % ) " "Info: Total interconnect delay = 1.161 ns ( 43.05 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.697 ns" { clk clk~clkctrl lockopen~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.697 ns" { clk clk~combout clk~clkctrl lockopen~reg0 } { 0.000ns 0.000ns 0.118ns 1.043ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.697 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.697 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "openlock.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/openlock/openlock.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G3 25 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 25; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "openlock.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/openlock/openlock.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.043 ns) + CELL(0.537 ns) 2.697 ns temp4\[2\] 3 REG LCFF_X28_Y35_N3 1 " "Info: 3: + IC(1.043 ns) + CELL(0.537 ns) = 2.697 ns; Loc. = LCFF_X28_Y35_N3; Fanout = 1; REG Node = 'temp4\[2\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.580 ns" { clk~clkctrl temp4[2] } "NODE_NAME" } } { "openlock.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/openlock/openlock.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 56.95 % ) " "Info: Total cell delay = 1.536 ns ( 56.95 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.161 ns ( 43.05 % ) " "Info: Total interconnect delay = 1.161 ns ( 43.05 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.697 ns" { clk clk~clkctrl temp4[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.697 ns" { clk clk~combout clk~clkctrl temp4[2] } { 0.000ns 0.000ns 0.118ns 1.043ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.697 ns" { clk clk~clkctrl lockopen~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.697 ns" { clk clk~combout clk~clkctrl lockopen~reg0 } { 0.000ns 0.000ns 0.118ns 1.043ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.697 ns" { clk clk~clkctrl temp4[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.697 ns" { clk clk~combout clk~clkctrl temp4[2] } { 0.000ns 0.000ns 0.118ns 1.043ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "openlock.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/openlock/openlock.vhd" 24 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "openlock.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/openlock/openlock.vhd" 24 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.447 ns" { temp4[2] lockopen~293 lockopen~295 lockopen~305 lockopen~306 lockopen~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.447 ns" { temp4[2] lockopen~293 lockopen~295 lockopen~305 lockopen~306 lockopen~reg0 } { 0.000ns 0.301ns 0.459ns 0.253ns 0.247ns 0.000ns } { 0.000ns 0.150ns 0.410ns 0.393ns 0.150ns 0.084ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.697 ns" { clk clk~clkctrl lockopen~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.697 ns" { clk clk~combout clk~clkctrl lockopen~reg0 } { 0.000ns 0.000ns 0.118ns 1.043ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.697 ns" { clk clk~clkctrl temp4[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.697 ns" { clk clk~combout clk~clkctrl temp4[2] } { 0.000ns 0.000ns 0.118ns 1.043ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "lockopen~reg0 code0\[2\] clk 6.288 ns register " "Info: tsu for register \"lockopen~reg0\" (data pin = \"code0\[2\]\", clock pin = \"clk\") is 6.288 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.021 ns + Longest pin register " "Info: + Longest pin to register delay is 9.021 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.842 ns) 0.842 ns code0\[2\] 1 PIN PIN_E5 2 " "Info: 1: + IC(0.000 ns) + CELL(0.842 ns) = 0.842 ns; Loc. = PIN_E5; Fanout = 2; PIN Node = 'code0\[2\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { code0[2] } "NODE_NAME" } } { "openlock.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/openlock/openlock.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.812 ns) + CELL(0.410 ns) 7.064 ns lockopen~297 2 COMB LCCOMB_X27_Y35_N20 1 " "Info: 2: + IC(5.812 ns) + CELL(0.410 ns) = 7.064 ns; Loc. = LCCOMB_X27_Y35_N20; Fanout = 1; COMB Node = 'lockopen~297'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.222 ns" { code0[2] lockopen~297 } "NODE_NAME" } } { "openlock.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/openlock/openlock.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.271 ns) + CELL(0.410 ns) 7.745 ns lockopen~300 3 COMB LCCOMB_X27_Y35_N2 1 " "Info: 3: + IC(0.271 ns) + CELL(0.410 ns) = 7.745 ns; Loc. = LCCOMB_X27_Y35_N2; Fanout = 1; COMB Node = 'lockopen~300'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.681 ns" { lockopen~297 lockopen~300 } "NODE_NAME" } } { "openlock.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/openlock/openlock.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.248 ns) + CELL(0.150 ns) 8.143 ns lockopen~301 4 COMB LCCOMB_X27_Y35_N30 1 " "Info: 4: + IC(0.248 ns) + CELL(0.150 ns) = 8.143 ns; Loc. = LCCOMB_X27_Y35_N30; Fanout = 1; COMB Node = 'lockopen~301'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.398 ns" { lockopen~300 lockopen~301 } "NODE_NAME" } } { "openlock.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/openlock/openlock.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.247 ns) + CELL(0.150 ns) 8.540 ns lockopen~305 5 COMB LCCOMB_X27_Y35_N10 1 " "Info: 5: + IC(0.247 ns) + CELL(0.150 ns) = 8.540 ns; Loc. = LCCOMB_X27_Y35_N10; Fanout = 1; COMB Node = 'lockopen~305'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.397 ns" { lockopen~301 lockopen~305 } "NODE_NAME" } } { "openlock.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/openlock/openlock.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.247 ns) + CELL(0.150 ns) 8.937 ns lockopen~306 6 COMB LCCOMB_X27_Y35_N0 1 " "Info: 6: + IC(0.247 ns) + CELL(0.150 ns) = 8.937 ns; Loc. = LCCOMB_X27_Y35_N0; Fanout = 1; COMB Node = 'lockopen~306'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.397 ns" { lockopen~305 lockopen~306 } "NODE_NAME" } } { "openlock.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/openlock/openlock.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 9.021 ns lockopen~reg0 7 REG LCFF_X27_Y35_N1 3 " "Info: 7: + IC(0.000 ns) + CELL(0.084 ns) = 9.021 ns; Loc. = LCFF_X27_Y35_N1; Fanout = 3; REG Node = 'lockopen~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { lockopen~306 lockopen~reg0 } "NODE_NAME" } } { "openlock.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/openlock/openlock.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.196 ns ( 24.34 % ) " "Info: Total cell delay = 2.196 ns ( 24.34 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.825 ns ( 75.66 % ) " "Info: Total interconnect delay = 6.825 ns ( 75.66 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.021 ns" { code0[2] lockopen~297 lockopen~300 lockopen~301 lockopen~305 lockopen~306 lockopen~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "9.021 ns" { code0[2] code0[2]~combout lockopen~297 lockopen~300 lockopen~301 lockopen~305 lockopen~306 lockopen~reg0 } { 0.000ns 0.000ns 5.812ns 0.271ns 0.248ns 0.247ns 0.247ns 0.000ns } { 0.000ns 0.842ns 0.410ns 0.410ns 0.150ns 0.150ns 0.150ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "openlock.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/openlock/openlock.vhd" 24 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.697 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.697 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "openlock.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/openlock/openlock.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G3 25 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 25; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "openlock.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/openlock/openlock.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.043 ns) + CELL(0.537 ns) 2.697 ns lockopen~reg0 3 REG LCFF_X27_Y35_N1 3 " "Info: 3: + IC(1.043 ns) + CELL(0.537 ns) = 2.697 ns; Loc. = LCFF_X27_Y35_N1; Fanout = 3; REG Node = 'lockopen~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.580 ns" { clk~clkctrl lockopen~reg0 } "NODE_NAME" } } { "openlock.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/openlock/openlock.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 56.95 % ) " "Info: Total cell delay = 1.536 ns ( 56.95 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.161 ns ( 43.05 % ) " "Info: Total interconnect delay = 1.161 ns ( 43.05 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.697 ns" { clk clk~clkctrl lockopen~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.697 ns" { clk clk~combout clk~clkctrl lockopen~reg0 } { 0.000ns 0.000ns 0.118ns 1.043ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.021 ns" { code0[2] lockopen~297 lockopen~300 lockopen~301 lockopen~305 lockopen~306 lockopen~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "9.021 ns" { code0[2] code0[2]~combout lockopen~297 lockopen~300 lockopen~301 lockopen~305 lockopen~306 lockopen~reg0 } { 0.000ns 0.000ns 5.812ns 0.271ns 0.248ns 0.247ns 0.247ns 0.000ns } { 0.000ns 0.842ns 0.410ns 0.410ns 0.150ns 0.150ns 0.150ns 0.084ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.697 ns" { clk clk~clkctrl lockopen~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.697 ns" { clk clk~combout clk~clkctrl lockopen~reg0 } { 0.000ns 0.000ns 0.118ns 1.043ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk lockclose lockopen~reg0 8.901 ns register " "Info: tco from clock \"clk\" to destination pin \"lockclose\" through register \"lockopen~reg0\" is 8.901 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.697 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.697 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "openlock.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/openlock/openlock.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G3 25 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 25; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "openlock.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/openlock/openlock.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.043 ns) + CELL(0.537 ns) 2.697 ns lockopen~reg0 3 REG LCFF_X27_Y35_N1 3 " "Info: 3: + IC(1.043 ns) + CELL(0.537 ns) = 2.697 ns; Loc. = LCFF_X27_Y35_N1; Fanout = 3; REG Node = 'lockopen~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.580 ns" { clk~clkctrl lockopen~reg0 } "NODE_NAME" } } { "openlock.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/openlock/openlock.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 56.95 % ) " "Info: Total cell delay = 1.536 ns ( 56.95 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.161 ns ( 43.05 % ) " "Info: Total interconnect delay = 1.161 ns ( 43.05 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.697 ns" { clk clk~clkctrl lockopen~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.697 ns" { clk clk~combout clk~clkctrl lockopen~reg0 } { 0.000ns 0.000ns 0.118ns 1.043ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "openlock.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/openlock/openlock.vhd" 24 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.954 ns + Longest register pin " "Info: + Longest register to pin delay is 5.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lockopen~reg0 1 REG LCFF_X27_Y35_N1 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X27_Y35_N1; Fanout = 3; REG Node = 'lockopen~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { lockopen~reg0 } "NODE_NAME" } } { "openlock.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/openlock/openlock.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.166 ns) + CELL(2.788 ns) 5.954 ns lockclose 2 PIN PIN_V14 0 " "Info: 2: + IC(3.166 ns) + CELL(2.788 ns) = 5.954 ns; Loc. = PIN_V14; Fanout = 0; PIN Node = 'lockclose'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.954 ns" { lockopen~reg0 lockclose } "NODE_NAME" } } { "openlock.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/openlock/openlock.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.788 ns ( 46.83 % ) " "Info: Total cell delay = 2.788 ns ( 46.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.166 ns ( 53.17 % ) " "Info: Total interconnect delay = 3.166 ns ( 53.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.954 ns" { lockopen~reg0 lockclose } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.954 ns" { lockopen~reg0 lockclose } { 0.000ns 3.166ns } { 0.000ns 2.788ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.697 ns" { clk clk~clkctrl lockopen~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.697 ns" { clk clk~combout clk~clkctrl lockopen~reg0 } { 0.000ns 0.000ns 0.118ns 1.043ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.954 ns" { lockopen~reg0 lockclose } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.954 ns" { lockopen~reg0 lockclose } { 0.000ns 3.166ns } { 0.000ns 2.788ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "lockopen~reg0 test clk 0.345 ns register " "Info: th for register \"lockopen~reg0\" (data pin = \"test\", clock pin = \"clk\") is 0.345 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.697 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.697 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "openlock.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/openlock/openlock.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G3 25 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 25; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "openlock.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/openlock/openlock.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.043 ns) + CELL(0.537 ns) 2.697 ns lockopen~reg0 3 REG LCFF_X27_Y35_N1 3 " "Info: 3: + IC(1.043 ns) + CELL(0.537 ns) = 2.697 ns; Loc. = LCFF_X27_Y35_N1; Fanout = 3; REG Node = 'lockopen~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.580 ns" { clk~clkctrl lockopen~reg0 } "NODE_NAME" } } { "openlock.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/openlock/openlock.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 56.95 % ) " "Info: Total cell delay = 1.536 ns ( 56.95 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.161 ns ( 43.05 % ) " "Info: Total interconnect delay = 1.161 ns ( 43.05 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.697 ns" { clk clk~clkctrl lockopen~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.697 ns" { clk clk~combout clk~clkctrl lockopen~reg0 } { 0.000ns 0.000ns 0.118ns 1.043ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "openlock.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/openlock/openlock.vhd" 24 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.618 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.618 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns test 1 PIN PIN_C13 2 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_C13; Fanout = 2; PIN Node = 'test'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { test } "NODE_NAME" } } { "openlock.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/openlock/openlock.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.118 ns) + CELL(0.437 ns) 2.534 ns lockopen~306 2 COMB LCCOMB_X27_Y35_N0 1 " "Info: 2: + IC(1.118 ns) + CELL(0.437 ns) = 2.534 ns; Loc. = LCCOMB_X27_Y35_N0; Fanout = 1; COMB Node = 'lockopen~306'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.555 ns" { test lockopen~306 } "NODE_NAME" } } { "openlock.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/openlock/openlock.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 2.618 ns lockopen~reg0 3 REG LCFF_X27_Y35_N1 3 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 2.618 ns; Loc. = LCFF_X27_Y35_N1; Fanout = 3; REG Node = 'lockopen~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { lockopen~306 lockopen~reg0 } "NODE_NAME" } } { "openlock.vhd" "" { Text "E:/SOPClab/digital_system_design/password_lock/openlock/openlock.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 57.30 % ) " "Info: Total cell delay = 1.500 ns ( 57.30 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.118 ns ( 42.70 % ) " "Info: Total interconnect delay = 1.118 ns ( 42.70 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.618 ns" { test lockopen~306 lockopen~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.618 ns" { test test~combout lockopen~306 lockopen~reg0 } { 0.000ns 0.000ns 1.118ns 0.000ns } { 0.000ns 0.979ns 0.437ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.697 ns" { clk clk~clkctrl lockopen~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.697 ns" { clk clk~combout clk~clkctrl lockopen~reg0 } { 0.000ns 0.000ns 0.118ns 1.043ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.618 ns" { test lockopen~306 lockopen~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.618 ns" { test test~combout lockopen~306 lockopen~reg0 } { 0.000ns 0.000ns 1.118ns 0.000ns } { 0.000ns 0.979ns 0.437ns 0.084ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
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