alarm_clock.map.rpt

电子闹钟：基于fpga的电子闹钟设计

; POWER_UP_LEVEL ; Low   ; -    ; i_current_time[2][2] ;
; POWER_UP_LEVEL ; Low   ; -    ; i_current_time[2][3] ;
; POWER_UP_LEVEL ; Low   ; -    ; i_current_time[3][0] ;
; POWER_UP_LEVEL ; Low   ; -    ; i_current_time[3][1] ;
; POWER_UP_LEVEL ; Low   ; -    ; i_current_time[3][2] ;
; POWER_UP_LEVEL ; Low   ; -    ; i_current_time[3][3] ;
+----------------+-------+------+----------------------+


+------------------------------------------+
; Source assignments for fq_divider:u7     ;
+----------------+-------+------+----------+
; Assignment     ; Value ; From ; To       ;
+----------------+-------+------+----------+
; POWER_UP_LEVEL ; Low   ; -    ; tout[0]  ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[1]  ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[2]  ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[3]  ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[4]  ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[5]  ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[6]  ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[7]  ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[8]  ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[9]  ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[10] ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[11] ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[12] ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[13] ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[14] ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[15] ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[16] ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[17] ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[18] ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[19] ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[20] ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[21] ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[22] ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[23] ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[24] ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[25] ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[26] ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[27] ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[28] ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[29] ;
; POWER_UP_LEVEL ; Low   ; -    ; tout[30] ;
+----------------+-------+------+----------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Mon Oct 06 16:53:05 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off alarm_clock -c alarm_clock
Info: Found 3 design units, including 1 entities, in source file alarm_clock.vhd
    Info: Found design unit 1: p_alarm
    Info: Found design unit 2: alarm_clock-behav
    Info: Found entity 1: alarm_clock
Info: Found 0 design units, including 0 entities, in source file p_alarm.vhd
Info: Found 2 design units, including 1 entities, in source file key_buffer/key_buffer.vhd
    Info: Found design unit 1: key_buffer-behav
    Info: Found entity 1: key_buffer
Info: Found 2 design units, including 1 entities, in source file fq_divider/fq_divider.vhd
    Info: Found design unit 1: fq_divider-behav
    Info: Found entity 1: fq_divider
Info: Found 2 design units, including 1 entities, in source file display_driver/display_driver.vhd
    Info: Found design unit 1: display_driver-behav
    Info: Found entity 1: display_driver
Info: Found 2 design units, including 1 entities, in source file decoder/decoder.vhd
    Info: Found design unit 1: decoder-behav
    Info: Found entity 1: decoder
Info: Found 2 design units, including 1 entities, in source file alarm_reg/alarm_reg.vhd
    Info: Found design unit 1: alarm_reg-behav
    Info: Found entity 1: alarm_reg
Info: Found 2 design units, including 1 entities, in source file alarm_counter/alarm_counter.vhd
    Info: Found design unit 1: alarm_counter-behav
    Info: Found entity 1: alarm_counter
Info: Found 2 design units, including 1 entities, in source file alarm_controller/alarm_controller.vhd
    Info: Found design unit 1: alarm_controller-behav
    Info: Found entity 1: alarm_controller
Info: Elaborating entity "alarm_clock" for the top level hierarchy
Info: Elaborating entity "decoder" for hierarchy "decoder:u1"
Info: Elaborating entity "key_buffer" for hierarchy "key_buffer:u2"
Info: Elaborating entity "alarm_controller" for hierarchy "alarm_controller:u3"
Info: Elaborating entity "alarm_counter" for hierarchy "alarm_counter:u4"
Warning (10492): VHDL Process Statement warning at alarm_counter.vhd(22): signal "new_current_time" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Elaborating entity "alarm_reg" for hierarchy "alarm_reg:u5"
Info: Elaborating entity "display_driver" for hierarchy "display_driver:u6"
Warning (10631): VHDL Process Statement warning at display_driver.vhd(20): inferring latch(es) for signal or variable "display_time", which holds its previous value in one or more paths through the process
Info (10041): Verilog HDL or VHDL info at display_driver.vhd(20): inferred latch for "display_time[0][0]"
Info (10041): Verilog HDL or VHDL info at display_driver.vhd(20): inferred latch for "display_time[0][1]"
Info (10041): Verilog HDL or VHDL info at display_driver.vhd(20): inferred latch for "display_time[0][2]"
Info (10041): Verilog HDL or VHDL info at display_driver.vhd(20): inferred latch for "display_time[0][3]"
Info (10041): Verilog HDL or VHDL info at display_driver.vhd(20): inferred latch for "display_time[1][0]"
Info (10041): Verilog HDL or VHDL info at display_driver.vhd(20): inferred latch for "display_time[1][1]"
Info (10041): Verilog HDL or VHDL info at display_driver.vhd(20): inferred latch for "display_time[1][2]"
Info (10041): Verilog HDL or VHDL info at display_driver.vhd(20): inferred latch for "display_time[1][3]"
Info (10041): Verilog HDL or VHDL info at display_driver.vhd(20): inferred latch for "display_time[2][0]"
Info (10041): Verilog HDL or VHDL info at display_driver.vhd(20): inferred latch for "display_time[2][1]"
Info (10041): Verilog HDL or VHDL info at display_driver.vhd(20): inferred latch for "display_time[2][2]"
Info (10041): Verilog HDL or VHDL info at display_driver.vhd(20): inferred latch for "display_time[2][3]"
Info (10041): Verilog HDL or VHDL info at display_driver.vhd(20): inferred latch for "display_time[3][0]"
Info (10041): Verilog HDL or VHDL info at display_driver.vhd(20): inferred latch for "display_time[3][1]"
Info (10041): Verilog HDL or VHDL info at display_driver.vhd(20): inferred latch for "display_time[3][2]"
Info (10041): Verilog HDL or VHDL info at display_driver.vhd(20): inferred latch for "display_time[3][3]"
Info: Elaborating entity "fq_divider" for hierarchy "fq_divider:u7"
Info: State machine "|alarm_clock|alarm_controller:u3|curr_state" contains 5 states
Info: Selected Auto state machine encoding method for state machine "|alarm_clock|alarm_controller:u3|curr_state"
Info: Encoding result for state machine "|alarm_clock|alarm_controller:u3|curr_state"
    Info: Completed encoding using 5 state bits
        Info: Encoded state bit "alarm_controller:u3|curr_state.s4"
        Info: Encoded state bit "alarm_controller:u3|curr_state.s3"
        Info: Encoded state bit "alarm_controller:u3|curr_state.s2"
        Info: Encoded state bit "alarm_controller:u3|curr_state.s1"
        Info: Encoded state bit "alarm_controller:u3|curr_state.s0"
    Info: State "|alarm_clock|alarm_controller:u3|curr_state.s0" uses code string "00000"
    Info: State "|alarm_clock|alarm_controller:u3|curr_state.s1" uses code string "00011"
    Info: State "|alarm_clock|alarm_controller:u3|curr_state.s2" uses code string "00101"
    Info: State "|alarm_clock|alarm_controller:u3|curr_state.s3" uses code string "01001"
    Info: State "|alarm_clock|alarm_controller:u3|curr_state.s4" uses code string "10001"
Info: Converted presettable and clearable register to equivalent circuits with latches. Registers will power-up to an undefined state, and DEVCLRn will place the registers in an undefined state.
    Info: Register "alarm_counter:u4|i_current_time[0][0]" converted into equivalent circuit using register "alarm_counter:u4|i_current_time[0][0]~$emulated" and latch "alarm_counter:u4|i_current_time[0][0]~490"
    Info: Register "alarm_counter:u4|i_current_time[0][1]" converted into equivalent circuit using register "alarm_counter:u4|i_current_time[0][1]~$emulated" and latch "alarm_counter:u4|i_current_time[0][1]~501"
    Info: Register "alarm_counter:u4|i_current_time[0][2]" converted into equivalent circuit using register "alarm_counter:u4|i_current_time[0][2]~$emulated" and latch "alarm_counter:u4|i_current_time[0][2]~512"
    Info: Register "alarm_counter:u4|i_current_time[0][3]" converted into equivalent circuit using register "alarm_counter:u4|i_current_time[0][3]~$emulated" and latch "alarm_counter:u4|i_current_time[0][3]~523"
    Info: Register "alarm_counter:u4|i_current_time[1][0]" converted into equivalent circuit using register "alarm_counter:u4|i_current_time[1][0]~$emulated" and latch "alarm_counter:u4|i_current_time[1][0]~534"
    Info: Register "alarm_counter:u4|i_current_time[1][1]" converted into equivalent circuit using register "alarm_counter:u4|i_current_time[1][1]~$emulated" and latch "alarm_counter:u4|i_current_time[1][1]~545"
    Info: Register "alarm_counter:u4|i_current_time[1][2]" converted into equivalent circuit using register "alarm_counter:u4|i_current_time[1][2]~$emulated" and latch "alarm_counter:u4|i_current_time[1][2]~556"
    Info: Register "alarm_counter:u4|i_current_time[1][3]" converted into equivalent circuit using register "alarm_counter:u4|i_current_time[1][3]~$emulated" and latch "alarm_counter:u4|i_current_time[1][3]~567"
    Info: Register "alarm_counter:u4|i_current_time[2][0]" converted into equivalent circuit using register "alarm_counter:u4|i_current_time[2][0]~$emulated" and latch "alarm_counter:u4|i_current_time[2][0]~578"
    Info: Register "alarm_counter:u4|i_current_time[2][1]" converted into equivalent circuit using register "alarm_counter:u4|i_current_time[2][1]~$emulated" and latch "alarm_counter:u4|i_current_time[2][1]~589"
    Info: Register "alarm_counter:u4|i_current_time[2][2]" converted into equivalent circuit using register "alarm_counter:u4|i_current_time[2][2]~$emulated" and latch "alarm_counter:u4|i_current_time[2][2]~600"
    Info: Register "alarm_counter:u4|i_current_time[2][3]" converted into equivalent circuit using register "alarm_counter:u4|i_current_time[2][3]~$emulated" and latch "alarm_counter:u4|i_current_time[2][3]~611"
    Info: Register "alarm_counter:u4|i_current_time[3][0]" converted into equivalent circuit using register "alarm_counter:u4|i_current_time[3][0]~$emulated" and latch "alarm_counter:u4|i_current_time[3][0]~622"
    Info: Register "alarm_counter:u4|i_current_time[3][1]" converted into equivalent circuit using register "alarm_counter:u4|i_current_time[3][1]~$emulated" and latch "alarm_counter:u4|i_current_time[3][1]~633"
    Info: Register "alarm_counter:u4|i_current_time[3][2]" converted into equivalent circuit using register "alarm_counter:u4|i_current_time[3][2]~$emulated" and latch "alarm_counter:u4|i_current_time[3][2]~644"
    Info: Register "alarm_counter:u4|i_current_time[3][3]" converted into equivalent circuit using register "alarm_counter:u4|i_current_time[3][3]~$emulated" and latch "alarm_counter:u4|i_current_time[3][3]~655"
Info: Implemented 358 device resources after synthesis - the final resource count might be different
    Info: Implemented 15 input pins
    Info: Implemented 29 output pins
    Info: Implemented 314 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings
    Info: Processing ended: Mon Oct 06 16:53:10 2008
    Info: Elapsed time: 00:00:06